Michele Stucchi

According to our database, Michele Stucchi authored at least 35 papers between 2002 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Backside Power Delivery with relaxed overlay for backside patterning using extreme wafer thinning and Molybdenum-filled slit nano Through Silicon Vias.

P. Zhao, Liesbeth Witters, Anne Jourdain, Michele Stucchi, Nicolas Jourdan, J. W. Maes, H. Bana, C. Zhu, R. Chukka, F. Sebaai, Kevin Vandersmissen, N. Heylen, D. Montero, S. Wang, K. D'Have, F. Schleicher, J. De Vos, Gerald Beyer, A. Miller, Eric Beyne

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2023

Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node.

Giuliano Sisto, R. Preston, Rongmei Chen, Gioele Mirabelli, Anita Farokhnejad, Yun Zhou, Ivan Ciofi, Anne Jourdain, A. Veloso, Michele Stucchi, Odysseas Zografos, Pieter Weckx, Geert Hellings, Julien Ryckaert

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures.

Francesco Lorenzelli, Asser Elsayed, Clement Godfrin, Alexander Grill, Stefan Kubicek, Ruoyu Li, Michele Stucchi, Danny Wan, Kristiaan De Greve, Erik Jan Marinissen, Georges G. E. Gielen

Proceedings of the IEEE International Test Conference, 2023

Study of Transistor Metrics for Room-Temperature Screening of Single Electron Transistors for Silicon Spin Qubit Applications.

Francesco Lorenzelli, Asser Elsayed, Clement Godfrin, Alexander Grill, Stefan Kubicek, Ruoyu Li, Michele Stucchi, Danny Wan, Kristiaan De Greve, Erik Jan Marinissen, Georges G. E. Gielen

Proceedings of the IEEE European Test Symposium, 2023

2022

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails.

Anabela Veloso, Anne Jourdain, D. Radisic, Rongmei Chen, G. Arutchelvan, B. O'Sullivan, Hiroaki Arimura, Michele Stucchi, An De Keersgieter, M. Hosseini, T. Hopf, K. D'Have, S. Wang, E. Dupuy, G. Mannaert, Kevin Vandersmissen, S. Iacovo, P. Marien, S. Choudhury, F. Schleicher, F. Sebaai, Yusuke Oniki, X. Zhou, A. Gupta, Tom Schram, B. Briggs, C. Lorant, E. Rosseel, Andriy Hikavyy, Roger Loo, J. Geypen, D. Batuk, G. T. Martinez, J. P. Soulie, Katia Devriendt, B. T. Chan, S. Demuynck, Gaspard Hiblot, Geert Van der Plas, Julien Ryckaert, Gerald Beyer, E. Dentoni Litta, Eric Beyne, Naoto Horiguchi

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node.

Rongmei Chen, Giuliano Sisto, Michele Stucchi, Anne Jourdain, Kenichi Miyaguchi, Pieter Schuddinck, P. Woeltgens, H. Lin, Naveen Kakarla, Anabela Veloso, Dragomir Milojevic, Odysseas Zografos, Pieter Weckx, Geert Hellings, Geert Van der Plas, Julien Ryckaert, Eric Beyne

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021

Localization of Electrical Defects in Hybrid Bonding Interconnect Structures by Scanning Photocapacitance Microscopy.

Kristof J. P. Jacobs, Michele Stucchi, Eric Beyne

IEEE Trans. Instrum. Meas., 2021

2020

Metal reliability mechanisms in Ruthenium interconnects.

Olalla Varela Pedreira, Michele Stucchi, Anshul Gupta, Victor Vega-Gonzalez, Marleen van der Veen, Stephane Lariviere, Christopher J. Wilson, Zsolt Tökei, Kristof Croes

Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Accurate Measurements of Small Resistances in Vertical Interconnects with Small Aspect Ratios.

Michele Stucchi, Ferenc Fodor, Erik Jan Marinissen

Proceedings of the IEEE European Test Symposium, 2020

2019

Understanding EM-Degradation Mechanisms in Metal Heaters Used for Si Photonics Applications.

Kris Croes, Veerle Simons, Sofie Beyne, Vladimir Cherman, Herman Oprins, Michele Stucchi, Philippe Absil, A. Glabman, Eric Wilcox

Proceedings of the IEEE International Reliability Physics Symposium, 2019

2018

Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits.

Erik Jan Marinissen, Ferenc Fodor, Arnita Podpod, Michele Stucchi, Yu-Rong Jian, Cheng-Wen Wu

Proceedings of the IEEE International Test Conference, 2018

TSV process-induced MOS reliability degradation.

Yunlong Li, Michele Stucchi, Stefaan Van Huylenbroeck, Geert Van der Plas, Gerald Beyer, Eric Beyne, Kristof Croes

Proceedings of the IEEE International Reliability Physics Symposium, 2018

2017

Lock-in thermal laser stimulation for non-destructive failure localization in 3-D devices.

Kristof J. P. Jacobs, T. Wang, Michele Stucchi, Mario Gonzalez, Kris Croes, Ingrid De Wolf, Eric Beyne

Microelectron. Reliab., 2017

2016

Reliability Challenges Related to TSV Integration and 3-D Stacking.

Kristof Croes, Joke De Messemaeker, Yunlong Li, Wei Guo, Olalla Varela Pedreira, Vladimir Cherman, Michele Stucchi, Ingrid De Wolf, Eric Beyne

IEEE Des. Test, 2016

Continuity and reliability assessment of a scalable 3×50μm and 2×40μm via-middle TSV module.

Stefaan Van Huylenbroeck, Yunlong Li, Michele Stucchi, Lieve Bogaerts, Joeri De Vos, Gerald Beyer, Eric Beyne, Mohand Brouri, Praveen Nalla, Sanjay Gopinath, Matthew Thorum, Joe Richardson, Jengyi Yu

Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015

Impact of interconnect multiple-patterning variability on SRAMs.

Ioannis Karageorgos, Michele Stucchi, Praveen Raghavan, Julien Ryckaert, Zsolt Tokei, Diederik Verkest, Rogier Baert, Sushil Sakhare, Wim Dehaene

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Reliability challenges for barrier/liner system in high aspect ratio through silicon vias.

Yunlong Li, Stefaan Van Huylenbroeck, Els Van Besien, Xiaoping Shi, Chen Wu, Michele Stucchi, Gerald Beyer, Eric Beyne, Ingrid De Wolf, Kristof Croes

Microelectron. Reliab., 2014

2012

Capacitance Measurements of Two-Dimensional and Three-Dimensional IC Interconnect Structures by Quasi-Static C-V Technique.

Michele Stucchi, Dimitrios Velenis, Guruprasad Katti

IEEE Trans. Instrum. Meas., 2012

2011

Fine grain thermal modeling and experimental validation of 3D-ICs.

Herman Oprins, Adi Srinivasan, Miroslav Cupák, Vladimir Cherman, Cristina Torregiani, Michele Stucchi, Geert Van der Plas, Paul Marchal, Bart Vandevelde, E. Cheng

Microelectron. J., 2011

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology.

Geert Van der Plas, Paresh Limaye, Igor Loi, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Antonio Pullini, Federico Angiolini, Luca Benini, Wim Dehaene, Youssef Travaly, Eric Beyne, Paul Marchal

IEEE J. Solid State Circuits, 2011

2010

Design issues and considerations for low-cost 3D TSV IC technology.

Geert Van der Plas, Paresh Limaye, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Domae Shinichi, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Wim Dehaene, Youssef Travaly, Pol Marchal, Eric Beyne

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

3D integration: Circuit design, test, and reliability challenges.

Nikolaos Minas, Ingrid De Wolf, Erik Jan Marinissen, Michele Stucchi, Herman Oprins, Abdelkarim Mercha, Geert Van der Plas, Dimitrios Velenis, Pol Marchal

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions.

Geert Van der Plas, Steven Thijs, Dimitri Linten, Guruprasad Katti, Paresh Limaye, Abdelkarim Mercha, Michele Stucchi, Herman Oprins, Bart Vandevelde, Nikolaos Minas, Miro Cupac, Morin Dehan, Marc Nelis, Rahul Agarwal, Wim Dehaene, Youssef Travaly, Eric Beyne, Paul Marchal

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009

3-D Technology Assessment: Path-Finding the Technology/Design Sweet-Spot.

Paul Marchal, Bruno Bougard, Guruprasad Katti, Michele Stucchi, Wim Dehaene, Antonis Papanikolaou, Diederik Verkest, Bart Swinnen, Eric Beyne

Proc. IEEE, 2009

Impact of 3D design choices on manufacturing cost.

Dimitrios Velenis, Michele Stucchi, Erik Jan Marinissen, Bart Swinnen, Eric Beyne

Proceedings of the IEEE International Conference on 3D System Integration, 2009

3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV).

Jan Van Olmen, Jan Coenen, Wim Dehaene, Kristin De Meyer, Cedric Huyghebaert, Anne Jourdain, Guruprasad Katti, Abdelkarim Mercha, Michal Rakowski, Michele Stucchi, Youssef Travaly, Eric Beyne, Bart Swinnen

Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008

A tool flow for predicting system level timing failures due to interconnect reliability degradation.

Jin Guo, Antonis Papanikolaou, Michele Stucchi, Kristof Croes, Zsolt Tokei, Francky Catthoor

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2006

Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies.

Evelyn Grossar, Michele Stucchi, Karen Maex, Wim Dehaene

IEEE J. Solid State Circuits, 2006

Impact of interconnect resistance increase on system performance of low power and high performance designs.

Mandeep Bamal, Youssef Travaly, Wenqi Zhang, Michele Stucchi, Karen Maex

Proceedings of the Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), 2006

Statistically Aware SRAM Memory Array Design.

Evelyn Grossar, Michele Stucchi, Karen Maex, Wim Dehaene

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

2004

Interconnect width selection for deep submicron designs using the table lookup method.

Mandeep Bamal, Evelyn Grossar, Michele Stucchi, Karen Maex

Proceedings of the Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), 2004

2003

Global interconnect trade-off for technology over memory modules to application level: case study.

Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex

Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003

2002

Frequency dependence in interline capacitance measurements.

Michele Stucchi, Karen Maex

IEEE Trans. Instrum. Meas., 2002

Interconnect exploration for future wire dominated technologies.

Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex

Proceedings of the Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), 2002

Simple and Efficient Approach for Shunt Admittance Parameters Calculations of VLSI On-Chip Interconnects on Semiconducting Substrate.

Hasan Ymeri, Bart Nauwelaers, Karen Maex, David De Roest, Michele Stucchi, Servaas Vandenberghe

Proceedings of the 2002 Design, 2002