Michele Borgatti

According to our database1, Michele Borgatti authored at least 24 papers between 1996 and 2005.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2005
Handling Different Computational Granularity by a Reconfigurable IC Featuring Embedded FPGAs and a Network-on-Chip.
Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

2004
A 0.13μm 1Gb/s/channel store-and-forward network on-chip.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

A Verification Methodology for Reconfigurable Systems.
Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004

An Integrated Design and Verification Methodology for Reconfigurable Multimedia Systems.
Proceedings of the 2004 Design, 2004

Platform IC with embedded via programmable logic for fast customization.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
A reconfigurable system featuring dynamically extensible embedded microprocessor, FPGA, and customizable I/O.
IEEE J. Solid State Circuits, 2003

Different Approaches to Add Reconfigurability in a SoC Architecture.
Proceedings of the 2003 Design, 2003

Application Mapping to a Hardware Platform through Automated Code Generation Targeting a RTOS: A Design Case Study.
Proceedings of the 2003 Design, 2003

A reconfigurable signal processing IC with embedded FPGA and multi-port flash memory.
Proceedings of the 40th Design Automation Conference, 2003

Application Mapping to a Hardware Platform Through Automated Code Generation Targeting a RTOS.
Proceedings of the Embedded Software for SoC, 2003

2002
A reconfigurable system featuring dynamically extensible embedded microprocessor, FPGA and customisable I/O.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2001
A 64-min single-chip voice recorder/player using embedded 4-b/cell flash memory.
IEEE J. Solid State Circuits, 2001

2000
A complete system for NN classification based on a VLSI array processor.
Pattern Recognit., 2000

A 64 min single-chip voice recorder/player using embedded 4 bit/cell flash memory.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1998
A Geometric Approach to Maximum-Speed n-Dimensional Continuous Linear Interpolation in Rectangular Grids.
IEEE Trans. Computers, 1998

A low-power integrated circuit for remote speech recognition.
IEEE J. Solid State Circuits, 1998

A low-power, voice-controlled, H.263 video decoder for portable applications.
IEEE J. Solid State Circuits, 1998

OMI-Compliant Model for Virtual Emulation.
Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping (RSP 1998), 1998

A low-power VLSI feature extractor for speech recognition.
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998

A 1 V, 25 μW speech recognizer for portable systems.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

1997
Fast board-level prototyping of a speech recognition system using virtual emulation.
Proceedings of the Proceedings 8th IEEE International Workshop on Rapid System Prototyping: Shortening the Path from Specification to Prototype, 1997

1996
A smoothly upgradable approach to virtual emulation of HW/SW systems.
Proceedings of the Seventh IEEE International Workshop on Rapid System Prototyping (RSP '96), 1996

A VLSI array processor accelerator for k-NN classification.
Proceedings of the 13th International Conference on Pattern Recognition, 1996

Extraction of LP-based features from one-bit quantized speech signals for recognition purposes.
Proceedings of the 8th European Signal Processing Conference, 1996


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