Michel Robert
Orcid: 0000-0002-5075-2898
According to our database1,
Michel Robert
authored at least 91 papers
between 1990 and 2023.
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Bibliography
2023
Sustain. Comput. Informatics Syst., January, 2023
Optimization of Data and Energy Migrations in Mini Data Centers for Carbon-Neutral Computing.
IEEE Trans. Sustain. Comput., 2023
2017
Proceedings of the IEEE Conference on Standards for Communications and Networking, 2017
2016
Proceedings of the IEEE 84th Vehicular Technology Conference, 2016
Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy Exploration.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016
Proceedings of the 2016 IEEE Conference on Standards for Communications and Networking, 2016
2015
Design Exploration for next Generation High-Performance Manycore On-chip Systems: Application to big.LITTLE Architectures.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
2013
Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach.
ACM Trans. Embed. Comput. Syst., 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
Int. J. Distributed Sens. Networks, 2012
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012
2011
Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization.
Microelectron. J., 2011
PI and PID Regulation Approaches for Performance-Constrained Adaptive Multiprocessor System-on-Chip.
IEEE Embed. Syst. Lett., 2011
Exploring dynamic mapping impact on NoC-based MPSoCs performance using a model-based framework.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011
Proceedings of the Multiprocessor System-on-Chip - Hardware Design and Tool Integration., 2011
2010
Int. J. Embed. Syst., 2010
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Proceedings of the VLSI-SoC: Forward-Looking Trends in IC and Systems Design, 2010
Providing Better Multi-processor Systems-on-Chip Resources Utilization by Means of Using a Control-Loop Feedback Mechanism.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
2009
Proceedings of the VLSI-SoC: Technologies for Systems Integration, 2009
Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the IEEE Congress on Evolutionary Computation, 2009
A Bio-Inspired Agent Framework for Hardware Accelerated Distributed Pervasive Applications.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2009
2008
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Statistical Sizing of an eSRAM Dummy Bitline Driver for Read Margin Improvement in the Presence of Variability Aspects.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
The Perplexus Programming Framework: Combining Bio-inspiration and Agent-Oriented Programming for the Simulation of Large Scale Complex Systems.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2008
BAF: A Bio-Inspired Agent Framework for Distributed Pervasive Applications.
Proceedings of the 2008 International Conference on Genetic and Evolutionary Methods, 2008
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008
2007
Proceedings of the IFIP VLSI-SoC 2007, 2007
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007
HS Scale: A run-time adaptable MP-SoC architecture.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007
2006
Proceedings of the IFIP VLSI-SoC 2006, 2006
A Parallel and Secure Architecture for Asymmetric Cryptography.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
Dynamic Hardware Multiplexing: Improving Adaptability with a Run Time Reconfiguration Manager.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006
Proceedings of the International Symposium on System-on-Chip, 2006
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006
2005
Méthode de caractérisation des architectures d'accélérateurs flexibles pour systèmes sur puce.
Tech. Sci. Informatiques, 2005
Distributed system design based on dependability evaluation: a case study on a pilot thermal process.
Reliab. Eng. Syst. Saf., 2005
J. Low Power Electron., 2005
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005
A new hardware countermeasure for masking power signatures of crypto cores.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005
Proceedings of the Integrated Circuit and System Design, 2005
Automatic Task Scheduling / Loop Unrolling using Dedicated RTR Controllers in Coarse Grain Reconfigurable Architectures.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
Test Engineering Education in Europe - The CRTC experience through the EuNICE-Test project.
Proceedings of the New Trends and Technologies in Computer-Aided Learning for Computer-Aided Design, 2005
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005
Proceedings of the Advanced Concepts for Intelligent Vision Systems, 2005
2004
Metrics for Digital Signal Processing Architectures Characterization: Remanence and Scalability.
Proceedings of the Computer Systems: Architectures, 2004
Proceedings of the Integrated Circuit and System Design, 2004
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
2003
Are coarse grain reconfigurable architectures suitable for cryptography?
Proceedings of the IFIP VLSI-SoC 2003, 2003
Metrics for Reconfigurable Architectures Characterization: Remanence and Scalability.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003
A Novel Approach for Architectural Model Characterization. An Example through the Systolic Ring.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003
2002
IEEE Trans. Educ., 2002
Iris recognition system for person identification.
Proceedings of the Pattern Recognition in Information Systems, 2002
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002
2001
Dynamically Reconfigurable Architectures for Digital Signal Processing Applications.
Proceedings of the SOC Design Methodologies, 2001
Proceedings of 8th IEEE International Conference on Emerging Technologies and Factory Automation, 2001
2000
Design of a Classification System for Rectangular Shapes Using a Co-Design Environment.
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000
Proceedings of the 2000 International Conference on Image Processing, 2000
1999
Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), 1999
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999
Embedded Systems Design And Verification: Reuse Oriented Prototyping Methodologies.
Proceedings of the VLSI: Systems on a Chip, 1999
A Virtual CMOS Library Approach for East Layout Synthesis.
Proceedings of the VLSI: Systems on a Chip, 1999
RF Interface Design Using Mixed-Mode Methodology.
Proceedings of the VLSI: Systems on a Chip, 1999
Implementation of a Wavelet Transform Architecture for Image Processing.
Proceedings of the VLSI: Systems on a Chip, 1999
1998
Real Time Imaging, 1998
1996
Proceedings of the Field-Programmable Logic, 1996
1995
Proceedings of the Proceedings EURO-DAC'95, 1995
1994
Proceedings of the Field-Programmable Logic, 1994
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994
1993
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993
1991
Microprocessing and Microprogramming, 1991
Proceedings of the conference on European design automation, 1991
1990
Proceedings of the European Design Automation Conference, 1990