Michel Haond

According to our database, Michel Haond authored at least 9 papers between 1999 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

Self-Heating in 28 FDSOI UTBB MOSFETs at Cryogenic Temperatures.

Lucas Nyssens, Arka Halder, Babak Kazemi Esfeh, Nicolas Planes, Michel Haond, Denis Flandre, Jean-Pierre Raskin, Valeriya Kilchytska

Proceedings of the 49th European Solid-State Device Research Conference, 2019

2017

Back-gate bias effect on UTBB-FDSOI non-linearity performance.

B. Kazemi Esfeh, Valeria Kilchytska, Bertrand Parvais, Nicolas Planes, M. Haond, Denis Flandre, Jean-Pierre Raskin

Proceedings of the 47th European Solid-State Device Research Conference, 2017

2016

Performance and layout effects of SiGe channel in 14nm UTBB FDSOI: SiGe-first vs. SiGe-last integration.

R. Berthelon, François Andrieu, P. Perreau, E. Baylac, A. Pofelski, Emmanuel Josse, Didier Dutartre, A. Claverie, Michel Haond

Proceedings of the 46th European Solid-State Device Research Conference, 2016

2015

Static and dynamic power management in 14nm FDSOI technology.

Olivier Weber, Emmanuel Josse, J. Mazurier, Michel Haond

Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Effective work function engineering by sacrificial lanthanum diffusion on HfON-based 14 nm NFET devices.

Carlos Suarez-Segovia, Charles Leroux, Florian Domengie, Karen Dabertrand, Vincent Joseph, Giovanni Romano, Pierre Caubet, Stephane Zoll, Olivier Weber, Gérard Ghibaudo, Gilles Reimbold, Michel Haond

Proceedings of the 45th European Solid State Device Research Conference, 2015

2014

Variability of UTBB MOSFET analog figures of merit in wide frequency range.

Sergej Makovejev, Babak Kazemi Esfeh, Jean-Pierre Raskin, Valeria Kilchytska, Denis Flandre, Vincent Barral, Nicolas Planes, Michel Haond

Proceedings of the 44th European Solid State Device Research Conference, 2014

Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs.

François Andrieu, Mikaël Cassé, E. Baylac, P. Perreau, O. Nier, Denis Rideau, R. Berthelon, Franck Pourchon, A. Pofelski, Barbara De Salvo, C. Gallon, Vincent Mazzocchi, D. Barge, C. Gaumer, O. Gourhant, A. Cros, Vincent Barral, Rossella Ranica, Nicolas Planes, Walter Schwarzenbach, E. Richard, Emmanuel Josse, Olivier Weber, Franck Arnaud, Maud Vinet, Olivier Faynot, Michel Haond

Proceedings of the 44th European Solid State Device Research Conference, 2014

2002

Validated 90nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC).

Thierry Devoivre, M. Lunenborg, C. Julien, J.-P. Carrere, P. Ferreira, W. J. Toren, A. VandeGoor, P. Gayet, T. Berger, O. Hinsinger, P. Vannier, Y. Trouiller, Y. Rody, P.-J. Goirand, R. Palla, I. Thomas, F. Guyader, David Roy, B. Borot, Nicolas Planes, Sylvie Naudet, F. Pico, D. Duca, F. Lalanne, D. Heslinga, M. Haond

Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002

1999

Developing a 0.18-micron CMOS process.

Michel Haond, Marie-Thérèse Basso, Walter deCoster, Jos Guelen, Christophe Lair

IEEE Micro, 1999