Michel Berkelaar

According to our database, Michel Berkelaar authored at least 11 papers between 2010 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2014

Considering Crosstalk Effects in Statistical Timing Analysis.

Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Statistical Transistor-Level Timing Analysis Using a Direct Random Differential Equation Solver.

Qin Tang, Javier Rodríguez, Amir Zjajo, Michel Berkelaar, Nick van der Meijs

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

2012

Direct Statistical Simulation of Timing Properties in Sequential Circuits.

Javier Rodríguez, Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

Transistor-level gate model based statistical timing analysis considering correlations.

Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Crosstalk-aware statistical interconnect delay calculation.

Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Stochastic Analysis of Deep-Submicrometer CMOS Process for Reliable Circuits Designs.

Amir Zjajo, Qin Tang, Michel Berkelaar, José Pineda de Gyvez, Alessandro Di Bucchianico, Nick van der Meijs

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Pseudo circuit model for representing uncertainty in waveforms.

Ashish Nigam, Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Statistical Moment Estimation of Delay and Power in Circuit Simulation.

Ashish Nigam, Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs

J. Low Power Electron., 2010

Transistor-Level Gate Modeling for Nano CMOS Circuit Verification Considering Statistical Process Variations.

Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

RDE-based transistor-level gate simulation for statistical static timing analysis.

Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs

Proceedings of the 47th Design Automation Conference, 2010

Noise analysis of non-linear dynamic integrated circuits.

Amir Zjajo, Qin Tang, Michel Berkelaar, Nick van der Meijs

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010