Michel A. Kinsy

Orcid: 0000-0002-1432-6939

According to our database1, Michel A. Kinsy authored at least 90 papers between 2007 and 2023.

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Bibliography

2023
Hardware Root-of-Trust Support for Operational Technology Cybersecurity in Critical Infrastructures.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2023

2022
Zeno: A Scalable Capability-Based Secure Architecture.
CoRR, 2022

A Compiler for Transparent Namespace-Based Access Control for the Zeno Architecture.
Proceedings of the 2022 IEEE International Symposium on Secure and Private Execution Environment Design (SEED), 2022

A Taxonomy of Error Sources in HPC I/O Machine Learning Models.
Proceedings of the SC22: International Conference for High Performance Computing, 2022

NeuroFabric: Hardware and ML Model Co-Design for A Priori Sparse Neural Network Training.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

2021
Security Threat Analyses and Attack Models for Approximate Computing Systems: From Hardware and Micro-architecture Perspectives.
ACM Trans. Design Autom. Electr. Syst., 2021

Adaptive caches as a defense mechanism against cache side-channel attacks.
J. Cryptogr. Eng., 2021

xBGAS: A Global Address Space Extension on RISC-V for High Performance Computing.
Proceedings of the 35th IEEE International Parallel and Distributed Processing Symposium, 2021

Reconfigurable Hardware Root-of-Trust for Secure Edge Processing.
Proceedings of the 2021 IEEE High Performance Extreme Computing Conference, 2021

Distributed Memory Guard: Enabling Secure Enclave Computing in NoC-based Architectures.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
Addressing a New Class of Reliability Threats in 3-D Network-on-Chips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Fast Arithmetic Hardware Library For RLWE-Based Homomorphic Encryption.
CoRR, 2020

NeuroFabric: Identifying Ideal Topologies for Training A Priori Sparse Networks.
CoRR, 2020

Gauge: An Interactive Data-Driven Visualization Tool for HPC Application I/O Performance Analysis.
Proceedings of the Fifth IEEE/ACM International Parallel Data Systems Workshop, 2020

HPC I/O throughput bottleneck analysis with explainable local models.
Proceedings of the International Conference for High Performance Computing, 2020

Toward Generalizable Models of I/O Throughput.
Proceedings of the 2020 IEEE/ACM International Workshop on Runtime and Operating Systems for Supercomputers, 2020

Quantum-Proof Lightweight McEliece Cryptosystem Co-processor Design.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Homomorphic Encryption Based Secure Sensor Data Processing.
Proceedings of the 2020 IEEE High Performance Extreme Computing Conference, 2020

A Hardware Root-of-Trust Design for Low-Power SoC Edge Devices.
Proceedings of the 2020 IEEE High Performance Extreme Computing Conference, 2020

A Post-Quantum Secure Discrete Gaussian Noise Sampler.
Proceedings of the 2020 IEEE International Symposium on Hardware Oriented Security and Trust, 2020

Towards Programmable All-Digital True Random Number Generator.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Fast Arithmetic Hardware Library For RLWE-Based Homomorphic Encryption.
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

Design-flow Methodology for Secure Group Anonymous Authentication.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Remote Atomic Extension (RAE) for Scalable High Performance Computing.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
Design Space Exploration of Neural Network Activation Function Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

SRASA: a Generalized Theoretical Framework for Security and Reliability Analysis in Computing Systems.
J. Hardw. Syst. Secur., 2019

Design of reliable storage and compute systems with lightweight group testing based non-binary error correction codes.
IET Comput. Digit. Tech., 2019

RASSS: a hijack-resistant confidential information management scheme for distributed systems.
IET Comput. Digit. Tech., 2019

Drndalo: Lightweight Control Flow Obfuscation Through Minimal Processor/Compiler Co-Design.
CoRR, 2019

Post-Quantum Cryptographic Hardware Primitives.
CoRR, 2019

A Lightweight McEliece Cryptosystem Co-processor Design.
CoRR, 2019

CodeTrolley: Hardware-Assisted Control Flow Obfuscation.
CoRR, 2019

Bulwark: Securing implantable medical devices communication channels.
Comput. Secur., 2019

A secure and robust scheme for sharing confidential information in IoT systems.
Ad Hoc Networks, 2019

The BRISC-V Platform: A Practical Teaching Approach for Computer Architecture.
Proceedings of the Workshop on Computer Architecture Education, 2019

Survey of Attacks and Defenses on Edge-Deployed Neural Networks.
Proceedings of the 2019 IEEE High Performance Extreme Computing Conference, 2019

A Survey on Hardware Security Techniques Targeting Low-Power SoC Designs.
Proceedings of the 2019 IEEE High Performance Extreme Computing Conference, 2019

Security Threats in Approximate Computing Systems.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Secure Computing Systems Design Through Formal Micro-Contracts.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Open-Source FPGA Implementation of Post-Quantum Cryptographic Hardware Primitives.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

BRISC-V: An Open-Source Architecture Design Space Exploration Toolbox.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

2018
Circuit enclaves susceptible to hardware Trojans insertion at gate-level designs.
IET Comput. Digit. Tech., 2018

Designing Secure Heterogeneous Multicore Systems from Untrusted Components.
Cryptogr., 2018

BRISC-V Emulator: A Standalone, Installation-Free, Browser-Based Teaching Tool.
CoRR, 2018

SAPA: Self-Aware Polymorphic Architecture.
CoRR, 2018

Sphinx: A Secure Architecture Based on Binary Code Diversification and Execution Obfuscation.
CoRR, 2018

ClosNets: a Priori Sparse Topologies for Faster DNN Training.
CoRR, 2018

Towards a Generalized Reconfigurable Agent-Based Architecture: Stock Market Simulation Acceleration.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

Adaptive and Dynamic Device Authentication Using Lorenz Chaotic Systems.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Mystic: Mystifying IP Cores Using an Always-ON FSM Obfuscation Method.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Application Specific Networks-on-Chip Synthesis: An Energy Efficient Approach.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

A Short Survey at the Intersection of Reliability and Security in Processor Architecture Designs.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

NoSync: Particle Swarm Inspired Distributed DNN Training.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2018, 2018

Chameleon: A Generalized Reconfigurable Open-Source Architecture for Deep Neural Network Training.
Proceedings of the 2018 IEEE High Performance Extreme Computing Conference, 2018

Scalable Open-Source Reconfigurable Architecture for Bacterial Quorum Sensing Simulations.
Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2018

Hardening AES Hardware Implementations Against Fault and Error Inject Attacks.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

ClosNets: Batchless DNN Training with On-Chip a Priori Sparse Neural Topologies.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Weighted Group Decision Making Using Multi-identity Physical Unclonable Functions.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Fast Dynamic Device Authentication Based on Lorenz Chaotic Systems.
Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018

Preventing Neural Network Model Exfiltration in Machine Learning Hardware Accelerators.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2018

2017
FASHION: Fault-Aware Self-Healing Intelligent On-chip Network.
CoRR, 2017

Fast Processing of Large Graph Applications Using Asynchronous Architecture.
CoRR, 2017

Adaptive Manycore Architectures for Big Data Computing.
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017

Advertiser elevator: A fault tolerant routing algorithm for partially connected 3D Network-on-Chips.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Janus: An uncertain cache architecture to cope with side channel attacks.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Crosstalk Free Coding Systems to Protect NoC Channels against Crosstalk Faults.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Hermes: Secure heterogeneous multicore architecture design.
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

PreNoc: Neural Network based Predictive Routing for Network-on-Chip Architectures.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

RASSS: A perfidy-aware protocol for designing trustworthy distributed systems.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

2016
A Deadlock-Free and Connectivity-Guaranteed Methodology for Achieving Fault-Tolerance in On-Chip Networks.
IEEE Trans. Computers, 2016

Fault-Aware Load-Balancing Routing for 2D-Mesh and Torus On-Chip Network Topologies.
IEEE Trans. Computers, 2016

Towards connectivity-guaranteed power-gating large-scale on-chip networks.
Proceedings of the Seventh International Green and Sustainable Computing Conference, 2016

2014
Algorithms for scheduling task-based applications onto heterogeneous many-core architectures.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2014

Low-overhead hard real-time aware interconnect network router.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2014

2013
Many-core architectures with time predictable execution Support for hard real-time applications.
PhD thesis, 2013

Optimal and Heuristic Application-Aware Oblivious Routing.
IEEE Trans. Computers, 2013

Heracles: a tool for fast RTL-based design space exploration of multicore processors.
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

MARTHA: architecture for control and emulation of power electronics and smart grid systems.
Proceedings of the Design, Automation and Test in Europe, 2013

2011
Brief announcement: distributed shared memory based on computation migration.
Proceedings of the SPAA 2011: Proceedings of the 23rd Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2011

Time-Predictable Computer Architecture for Cyber-Physical Systems: Digital Emulation of Power Electronics Systems.
Proceedings of the 32nd IEEE Real-Time Systems Symposium, 2011

HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

Heracles: Fully Synthesizable Parameterized MIPS-Based Multicore System.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

2009
Static virtual channel allocation in oblivious routing.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

Path-based, randomized, oblivious, minimal routing.
Proceedings of the Second International Workshop on Network on Chip Architectures, 2009

Application-aware deadlock-free oblivious routing.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

Oblivious Routing in On-Chip Bandwidth-Adaptive Networks.
Proceedings of the PACT 2009, 2009

2008
Diastolic arrays: throughput-driven reconfigurable computing.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

2007
ProtocolDB: Storing Scientific Protocols with a Domain Ontology.
Proceedings of the Web Information Systems Engineering - WISE 2007 Workshops, 2007

Storing Efficiently Bioinformatics Workflows.
Proceedings of the 7th IEEE International Conference on Bioinformatics and Bioengineering, 2007

Storing and Discovering Critical Workflows from Log in Scientific Exploration.
Proceedings of the 2007 IEEE International Conference on Services Computing, 2007


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