Michaela Brunner

Orcid: 0000-0001-7341-9812

According to our database1, Michaela Brunner authored at least 11 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Fault-Simulation-Based Flip-Flop Classification for Reverse Engineering.
Proceedings of the 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems, 2024

Hardware Honeypot: Setting Sequential Reverse Engineering on a Wrong Track.
Proceedings of the 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems, 2024

ScanCamouflage: Obfuscating Scan Chains with Camouflaged Sequential and Logic Gates.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
VE-FIDES: Designing Trustworthy Supply Chains Using Innovative Fingerprinting Implementations.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
Toward a Human-Readable State Machine Extraction.
ACM Trans. Design Autom. Electr. Syst., 2022

Open Source Hardware Design and Hardware Reverse Engineering: A Security Analysis.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

2020
TimingCamouflage+: Netlist Security Enhancement With Unconventional Timing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing (with Appendix).
CoRR, 2020

Logic Locking Induced Fault Attacks.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Timing Resilience for Efficient and Secure Circuits.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Improving on State Register Identification in Sequential Hardware Reverse Engineering.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019


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