Michael Witterauf

According to our database1, Michael Witterauf authored at least 22 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2024
ALPACA: An Accelerator Chip for Nested Loop Programs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2021
A Compiler for Symbolic Code Generation for Tightly Coupled Processor Arrays.
PhD thesis, 2021

Symbolic Loop Compilation for Tightly Coupled Processor Arrays.
ACM Trans. Embed. Comput. Syst., 2021

*-Predictable MPSoC execution of real-time control applications using invasive computing.
Concurr. Comput. Pract. Exp., 2021

Aarith: an arbitrary precision number library.
Proceedings of the SAC '21: The 36th ACM/SIGAPP Symposium on Applied Computing, 2021

2020
Real-time Scheduling of I/O Transfers for Massively Parallel Processor Arrays.
Proceedings of the 18th ACM/IEEE International Conference on Formal Methods and Models for System Design, 2020

Anytime Floating-Point Addition and Multiplication-Concepts and Implementations.
Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020

2019
Efficient Mapping of CNNs onto Tightly Coupled Processor Arrays.
J. Comput., 2019

Polyhedral fragments: an efficient representation for symbolically generating code for processor arrays.
Proceedings of the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design, 2019

Anytime instructions for programmable accuracy floating-point arithmetic.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

2018
Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays.
ACM Trans. Embed. Comput. Syst., 2018

Run-time Requirement Enforcement for Loop Programs on Processor Arrays.
Proceedings of the 16th ACM/IEEE International Conference on Formal Methods and Models for System Design, 2018

Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

2017
Constructing fast and cycle-accurate simulators for configurable accelerators using C++ templates.
Proceedings of the International Symposium on Rapid System Prototyping, 2017

2016
Providing fault tolerance through invasive computing.
it Inf. Technol., 2016

Modulo scheduling of symbolically tiled loops for tightly coupled processor arrays.
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2015
Techniques for on-demand structural redundancy for massively parallel processor arrays.
J. Syst. Archit., 2015

Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays.
Proceedings of the 13. ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2015

On-demand fault-tolerant loop processing on massively parallel processor arrays.
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

Adaptive fault tolerance through invasive computing.
Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015

A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays.
Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015

2014
Symbolic inner loop parallelisation for massively parallel processor arrays.
Proceedings of the Twelfth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2014


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