Michael T. Niemier

Hamza Errahmouni Barkam

CoRR, 2024

Shared-PIM: Enabling Concurrent Computation and Data Flow for Faster Processing-in-DRAM.

[BibT_eX]

[DOI]

CoRR, 2024

A New Secure Memory System for Efficient Data Protection and Access Pattern Obfuscation.

[BibT_eX]

[DOI]

CoRR, 2024

Efficient approximation of Earth Mover's Distance Based on Nearest Neighbor Search.

[BibT_eX]

[DOI]

CoRR, 2024

Design of High-Performance and Compact CAM for Supporting Data-Intensive Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Smoothing Disruption Across the Stack: Tales of Memory, Heterogeneity, & Compilers.

[BibT_eX]

[DOI]

João Paulo C. de Lima

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

A Reconfigurable FeFET Content Addressable Memory for Multi-State Hamming Distance.

[BibT_eX]

[DOI]

Ramin Rajaei

IEEE Trans. Circuits Syst. I Regul. Pap., 2023

Privacy Preserving In-memory Computing Engine.

[BibT_eX]

[DOI]

CoRR, 2023

Accelerating Polynomial Modular Multiplication with Crossbar-Based Compute-in-Memory.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Invited Paper: Algorithm/Hardware Co-Design for Few-Shot Learning at the Edge.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Cross Layer Design for the Predictive Assessment of Technology-Enabled Architectures.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

In-Memory Computing Accelerators for Emerging Learning Paradigms.

[BibT_eX]

[DOI]

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

IMCRYPTO: An In-Memory Computing Fabric for AES Encryption and Decryption.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2022

FeFET Multi-Bit Content-Addressable Memories for In-Memory Nearest Neighbor Search.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2022

Computing-In-Memory Using Ferroelectrics: From Single- to Multi-Input Logic.

[BibT_eX]

[DOI]

IEEE Des. Test, 2022

Experimentally realized memristive memory augmented neural network.

[BibT_eX]

[DOI]

CoRR, 2022

CoursePathVis: Course path visualization using flexible grouping and funnel-augmented Sankey diagram.

[BibT_eX]

[DOI]

Proceedings of the Visualization and Data Analysis 2022, online, January 15-26, 2022, 2022

COSIME: FeFET Based Associative Memory for In-Memory Cosine Similarity Search.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Eva-CAM: A Circuit/Architecture-Level Evaluation Tool for General Content Addressable Memories.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

iMARS: an in-memory-computing architecture for recommendation systems.

[BibT_eX]

[DOI]

Mengyuan Li

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

Deep Random Forest with Ferroelectric Analog Content Addressable Memory.

[BibT_eX]

[DOI]

Franz Müller

CoRR, 2021

Application-driven Design Exploration for Dense Ferroelectric Embedded Non-volatile Memories.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021

MIMHD: Accurate and Efficient Hyperdimensional Inference Using Multi-Bit In-Memory Computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021

A Flash-Based Multi-Bit Content-Addressable Memory with Euclidean Squared Distance.

[BibT_eX]

[DOI]

Shubham Sahay

Ayush Saxena

X. Sharon Hu

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021

Low-Cost Sequential Logic Circuit Design Considering Single Event Double-Node Upsets and Single Event Transients.

[BibT_eX]

[DOI]

Ramin Rajaei

Proceedings of the 39th IEEE International Conference on Computer Design, 2021

ICCAD Tutorial Session Paper Ferroelectric FET Technology and Applications: From Devices to Systems.

[BibT_eX]

[DOI]

Kai Ni

Simon Thomann

Cheng Zhuo

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Exploiting FeFETs via Cross-Layer Design from In-memory Computing Circuits to Meta-Learning Applications.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

In-Memory Computing based Accelerator for Transformer Networks for Long Sequences.

[BibT_eX]

[DOI]

X. Sharon Hu

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

In-Memory Nearest Neighbor Search with FeFET Multi-Bit Content-Addressable Memories.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Attention-in-Memory for Few-Shot Learning with Configurable Ferroelectric FET Arrays.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

Cross-layer Design for Computing-in-Memory: From Devices, Circuits, to Architectures and Applications.

[BibT_eX]

[DOI]

Hussam Amrouch

Mohsen Imani

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

Computing-in-Memory for Performance and Energy-Efficient Homomorphic Encryption.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

SearcHD: A Memory-Centric Hyperdimensional Computing With Stochastic Training.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Algorithmic Acceleration of B/FV-like Somewhat Homomorphic Encryption for Compute-Enabled RAM.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2020

The Impact of Ferroelectric FETs on Digital and Analog Circuits and Architectures.

[BibT_eX]

[DOI]

IEEE Des. Test, 2020

FeCAM: A Universal Compact Digital and Analog Content Addressable Memory Using Ferroelectric.

[BibT_eX]

[DOI]

CoRR, 2020

GC-eDRAM design using hybrid FinFET/NC-FinFET.

[BibT_eX]

[DOI]

Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

Embedding error correction into crossbars for reliable matrix vector multiplication using emerging devices.

[BibT_eX]

[DOI]

Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

Dynamic Memory and Sequential Logic Design using Negative Capacitance FinFETs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A Hybrid FeMFET-CMOS Analog Synapse Circuit for Neural Network Training and Inference.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Seed-and-Vote based In-Memory Accelerator for DNA Read Mapping.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Modeling and Benchmarking Computing-in-Memory for Design Space Exploration.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

AxR-NN: Approximate Computation Reuse for Energy-Efficient Convolutional Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

A Novel TIGFET-based DFF Design for Improved Resilience to Power Side-Channel Attacks.

[BibT_eX]

[DOI]

Ramin Rajaei

Patsy Cadareanu

Yier Jin

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

A Fast and Energy Efficient Computing-in-Memory Architecture for Few-Shot Learning Applications.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Emerging Neural Workloads and Their Impact on Hardware.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

A Device Non-Ideality Resilient Approach for Mapping Neural Networks to Crossbar Arrays.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Ferroelectric FETs-Based Nonvolatile Logic-in-Memory Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

An Ultra-Dense 2FeFET TCAM Design Based on a Multi-Domain FeFET Model.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2019

Power and Area Efficient FPGA Building Blocks Based on Ferroelectric FETs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Mixed Signal Architecture for Convolutional Neural Networks.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2019

A Survey on Architecture Advances Enabled by Emerging Beyond-CMOS Technologies.

[BibT_eX]

[DOI]

Tajana Simunic Rosing

J. Joshua Yang

IEEE Des. Test, 2019

Guest Editors' Introduction: Special Issue on Architecture Advances Enabled by Emerging Technologies.

[BibT_eX]

[DOI]

IEEE Des. Test, 2019

Nonvolatile Spintronic Memory Cells for Neural Networks.

[BibT_eX]

[DOI]

CoRR, 2019

Application-level Studies of Cellular Neural Network-based Hardware Accelerators.

[BibT_eX]

[DOI]

CoRR, 2019

Ferroelectric FET Based TCAM Designs for Energy Efficient Computing.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

A Uniform Modeling Methodology for Benchmarking DNN Accelerators.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

The Impact of Emerging Technologies on Architectures and System-level Management: Invited Paper.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

Ferroelectric FET Based In-Memory Computing for Few-Shot Learning.

[BibT_eX]

[DOI]

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

An Energy Efficient Non-Volatile Flip-Flop based on CoMET Technology.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Design of Hardware-Friendly Memory Enhanced Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

Cross-layer efforts for energy-efficient computing: towards peta operations per second per watt.

[BibT_eX]

[DOI]

Frontiers Inf. Technol. Electron. Eng., 2018

Can beyond-CMOS devices illuminate dark silicon?

[BibT_eX]

[DOI]

Commun. ACM, 2018

Computing in memory with FeFETs.

[BibT_eX]

[DOI]

Dayane Alfenas Reis

Proceedings of the International Symposium on Low Power Electronics and Design, 2018

Nonvolatile Lookup Table Design Based on Ferroelectric Field-Effect Transistors.

[BibT_eX]

[DOI]

Xiaoming Chen

Sandeep Krishna Thirumala

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Design and optimization of FeFET-based crossbars for binary convolution neural networks.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Computing with ferroelectric FETs: Devices, models, systems, and applications.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Biomedical Image Segmentation Using Fully Convolutional Networks on TrueNorth.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE International Symposium on Computer-Based Medical Systems, 2018

2017

Tunnel FET Current Mode Logic for DPA-Resilient Circuit Designs.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2017

Exploiting Non-Volatility for Information Processing.

[BibT_eX]

[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Design and benchmarking of ferroelectric FET based TCAM.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Advanced spintronic memory and logic for non-volatile processors.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Cellular neural network friendly convolutional neural networks - CNNs with CNNs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

In Quest of the Next Information Processing Substrate: Extended Abstract: Invited.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

Emerging Technology-Based Design of Primitives for Hardware Security.

[BibT_eX]

[DOI]

Yu Bi

Kaveh Shamsi

Jiann-Shiun Yuan

ACM J. Emerg. Technol. Comput. Syst., 2016

Molecular cellular networks: A non von Neumann architecture for molecular electronics.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Rebooting Computing, 2016

Exploiting ferroelectric FETs for low-power non-volatile logic-in-memory circuits.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Enhancing Hardware Security with Emerging Transistor Technologies.

[BibT_eX]

[DOI]

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Design of latches and flip-flops using emerging tunneling devices.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Using emerging technologies for hardware security beyond PUFs.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

Analog Circuit Design Using Tunnel-FETs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Reliable and high performance STT-MRAM architectures based on controllable-polarity devices.

[BibT_eX]

[DOI]

Kaveh Shamsi

Yu Bi

Yier Jin

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Analytically Modeling Power and Performance of a CNN System.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

TFET-based Operational Transconductance Amplifier Design for CNN Systems.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

A CNN-inspired mixed signal processor based on tunnel transistors.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Towards systematic design of 3D pNML layouts.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Nanomagnet Logic (NML).

[BibT_eX]

[DOI]

Proceedings of the Field-Coupled Nanocomputing - Paradigms, Progress, and Perspectives, 2014

Nontraditional Computation Using Beyond-CMOS Tunneling Devices.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

Understanding the landscape of accelerators for vision.

[BibT_eX]

[DOI]

Nandhini Chandramoorthy

Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Architectural impacts of emerging transistors.

[BibT_eX]

[DOI]

Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Boolean circuit design using emerging tunneling devices.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Cellular neural networks for image analysis using steep slope devices.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Design of 3D nanomagnetic logic circuits: A full-adder case study.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Impact of steep-slope transistors on non-von Neumann architectures: CNN case study.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Leveraging Emerging Technology for Hardware Security - Case Study on Silicon Nanowire FETs and Graphene SymFETs.

[BibT_eX]

[DOI]

Yu Bi

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

TFET-based cellular neural network architectures.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Systematic design of nanomagnet logic circuits.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Minimum-energy state guided physical design for nanomagnet logic.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

GPU acceleration of Data Assembly in Finite Element Methods and its energy implications.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012

A Reconfigurable PLA Architecture for Nanomagnet Logic.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2012

Network on metachip architectures.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Workshop on Network on Chip Architectures, 2012

Making non-volatile nanomagnet logic non-volatile.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011

Performance and Energy Impact of Locally Controlled NML Circuits.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2011

2010

Design and comparison of NML systolic architectures.

[BibT_eX]

[DOI]

Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

2009

Defects and faults in QCA-based PLAs.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2009

System-level energy and performance projections for nanomagnet-based logic.

[BibT_eX]

[DOI]

Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009

Controlling Magnetic Circuits: How Clock Structure Implementation will Impact Logical Correctness and Power.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008

Molecular QCA design with chemically reasonable constraints.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2008

Defect tolerance in QCA-based PLAs.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures, 2008

Bridging the gap between nanomagnetic devices and circuits.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Computer Design, 2008

Fabrication Variations and Defect Tolerance for Nanomagnet-Based QCA.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Design and defect tolerance beyond CMOS.

[BibT_eX]

[DOI]

Alexander Khitun

Konstantin K. Likharev

Mingqiang Bao

Kang L. Wang

Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

2007

Fabricatable Interconnect and Molecular QCA Circuits.

[BibT_eX]

[DOI]

Kevin Whitton

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Approximating the Maximum Sharing Problem.

[BibT_eX]

[DOI]

Proceedings of the Algorithms and Data Structures, 10th International Workshop, 2007

Clocking structures and power analysis for nanomagnet-based logic devices.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Fault Models and Yield Analysis for QCA-based PLAs.

[BibT_eX]

[DOI]

Proceedings of the FPL 2007, 2007

2006

PLAs in Quantum-dot Cellular Automata.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Using CAD to shape experiments in molecular QCA.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

2005

Partitioning and placement for buildable QCA circuits.

[BibT_eX]

[DOI]

Sung Kyu Lim

ACM J. Emerg. Technol. Comput. Syst., 2005

Automatic cell placement for quantum-dot cellular automata.

[BibT_eX]

[DOI]

Sung Kyu Lim

Integr., 2005

Eliminating wire crossings for molecular quantum-dot cellular automata implementation.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

2004

The "4-Diamond Circuit" - A Minimally Complex Nano-Scale Computational Building Block in QCA.

[BibT_eX]

[DOI]

Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Using Circuits and Systems-Level Research to Drive Nanotechnology.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Automatic cell placement for quantum-dot cellular automata.

[BibT_eX]

[DOI]

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Quantum-Dot Cellular Automata (QCA) circuit partitioning: problem modeling and solutions.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

2002

Teaching students computer architecture for new, nanotechnologies.

[BibT_eX]

[DOI]

Michael Thaddeus Niemier

Proceedings of the 2002 workshop on Computer architecture education, 2002

2001

Problems in designing with QCAs: Layout = Timing.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2001

Petaflop Computing for Protein Folding.

[BibT_eX]

Proceedings of the Tenth SIAM Conference on Parallel Processing for Scientific Computing, 2001

Exploring and exploiting wire-level pipelining in emerging technologies.

[BibT_eX]

[DOI]

Proceedings of the 28th Annual International Symposium on Computer Architecture, 2001

2000

A design of and design tools for a novel quantum dot based microprocessor.

[BibT_eX]

[DOI]

Michael J. Kontz

Proceedings of the 37th Conference on Design Automation, 2000

1999

Logic in wire: using quantum dots to implement a microprocessor.

[BibT_eX]

[DOI]