Michael Shebanow
According to our database1,
Michael Shebanow
authored at least 14 papers
between 1985 and 2016.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2015, "For contributions to superscalar out-of-order processors".
Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
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Bibliography
2016
Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor.
IEEE Micro, 2016
2013
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013
2011
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011
2009
Proceedings of the 6th Conference on Computing Frontiers, 2009
1995
Implementation Trade-Offs in Using a Restricted Data Flow Architecture in a High Performance RISC Microprocessor.
Proceedings of the 22nd Annual International Symposium on Computer Architecture, 1995
1991
Proceedings of the 18th Annual International Symposium on Computer Architecture. Toronto, 1991
1988
Proceedings of the 21st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1988, San Diego, California, USA, November 28, 1988
1987
Proceedings of the 20st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1987
1986
Proceedings of the 19th annual workshop on Microprogramming, 1986
Experiments with HPS, a Restricted Data Flow Microarchitecture for High Performance Computers.
Proceedings of the Spring COMPCON'86, 1986
1985
Proceedings of the 18th annual workshop on Microprogramming, 1985
Proceedings of the 18th annual workshop on Microprogramming, 1985