Michael Schaffner
Orcid: 0000-0002-3244-2693
According to our database1,
Michael Schaffner
authored at least 36 papers
between 1996 and 2022.
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Bibliography
2022
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022
2020
Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI.
IEEE Trans. Very Large Scale Integr. Syst., 2020
XwattPilot: A Full-stack Cloud System Enabling Agile Development of Transprecision Software for Low-power SoCs.
Proceedings of the 2020 IEEE Symposium in Low-Power and High-Speed Chips, 2020
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020
2019
IEEE Trans. Instrum. Meas., 2019
A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets.
IEEE Trans. Computers, 2019
Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22 nm FD-SOI.
CoRR, 2019
Proceedings of the International Conference for High Performance Computing, 2019
NTX: A 260 Gflop/sW Streaming Accelerator for Oblivious Floating-Point Algorithms in 22 nm FD-SOI.
Proceedings of the 2019 International SoC Design Conference, 2019
NTX: An Energy-efficient Streaming Accelerator for Floating-point Generalized Reduction Workloads in 22 nm FD-SOI.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
PhD thesis, 2018
IEEE Trans. Image Process., 2018
IEEE Trans. Instrum. Meas., 2018
NTX: An Energy-efficient Streaming Accelerator for Floating-point Generalized Reduction Workloads in 22nm FD-SOI.
CoRR, 2018
CoRR, 2018
Proceedings of the 2018 IEEE Sensors Applications Symposium, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
An Extended Shared Logarithmic Unit for Nonlinear Function Kernel Acceleration in a 65-nm CMOS Multicore Cluster.
IEEE J. Solid State Circuits, 2017
Impact of temporal subsampling on accuracy and performance in practical video classification.
Proceedings of the 25th European Signal Processing Conference, 2017
2016
Hybrid ASIC/FPGA System for Fully Automatic Stereo-to-Multiview Conversion Using IDW.
IEEE Trans. Circuits Syst. Video Technol., 2016
4.6 A 65nm CMOS 6.4-to-29.2pJ/FLOP@0.8V shared logarithmic floating point unit for acceleration of nonlinear function kernels in a tightly coupled processor cluster.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
High-efficiency logarithmic number unit design based on an improved cotransformation scheme.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Accuracy and Performance Trade-Offs of Logarithmic Number Units in Multi-Core Clusters.
Proceedings of the 23nd IEEE Symposium on Computer Arithmetic, 2016
2015
Proceedings of the 2015 Visual Communications and Image Processing, 2015
Proceedings of the 2015 Visual Communications and Image Processing, 2015
DRAM or no-DRAM?: exploring linear solver architectures for image domain warping in 28 nm CMOS.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
An Approximate Computing Technique for Reducing the Complexity of a Direct-Solver for Sparse Linear Systems in Real-Time Video Processing.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
A Complete Real-Time Feature Extraction and Matching System Based on Semantic Kernels Binarized.
Proceedings of the VLSI-SoC: At the Crossroads of Emerging Trends, 2013
Proceedings of the IEEE International Conference on Acoustics, 2013
MADmax: A 1080p stereo-to-multiview rendering ASIC in 65 nm CMOS based on image domain warping.
Proceedings of the ESSCIRC 2013, 2013
2012
Analysis and VLSI Implementation of EWA Rendering for Real-Time HD Video Applications.
IEEE Trans. Circuits Syst. Video Technol., 2012
Proceedings of the VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 2012
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012
1996
Methoden zur automatischen Generierung von Simulationsmodellen für ASIC-Bibliotheken.
Mainz, ISBN: 978-3-89653-054-7, 1996