Michael S. Hsiao

Proceedings of the Fourth International Conference on Transdisciplinary AI, 2022

Automated Suggestions Framework for Processing Hardware Specifications Written in English.

[BibT_eX]

[DOI]

Proceedings of the Forum on Specification & Design Languages, 2022

Hybrid Rule-based and Machine Learning System for Assertion Generation from Natural Language Specifications.

[BibT_eX]

[DOI]

Aditi

Proceedings of the IEEE 31st Asian Test Symposium, 2022

2021

Formal Validation for Natural Language Programming using Hierarchical Finite State Automata.

[BibT_eX]

Proceedings of the 13th International Conference on Agents and Artificial Intelligence, 2021

2020

Automated Assertion Generation from Natural Language Specifications.

[BibT_eX]

[DOI]

Steven J. Frederiksen

John Aromando

Proceedings of the IEEE International Test Conference, 2020

Transforming Natural Language Specifications to Logical Forms for Hardware Verification.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Breaking Down High-Level Robot Path-Finding Abstractions in Natural Language Programming.

[BibT_eX]

[DOI]

Proceedings of the AIxIA 2020 - Advances in Artificial Intelligence, 2020

2019

Controlled Natural Language Framework for Generating Assertions from Hardware Specifications.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Semantic Computing, 2019

EASE: Enabling Hardware Assertion Synthesis from English.

[BibT_eX]

[DOI]

Proceedings of the Rules and Reasoning - Third International Joint Conference, 2019

2018

Fast fault coverage estimation of sequential tests using entropy measurements.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE VLSI Test Symposium, 2018

An online framework for diagnosis of multiple defects in scan chains.

[BibT_eX]

[DOI]

Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Optimization of Mutant Space for RTL Test Generation.

[BibT_eX]

[DOI]

Kunal Bansal

Proceedings of the 36th IEEE International Conference on Computer Design, 2018

Automated Program Synthesis from Object-Oriented Natural Language for Computer Games.

[BibT_eX]

[DOI]

Proceedings of the Controlled Natural Language, 2018

A Natural Language Programming Application for Lego Mindstorms EV3.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Conference on Artificial Intelligence and Virtual Reality, 2018

2017

A framework for fast test generation at the RTL.

[BibT_eX]

[DOI]

Akash Agrawal

Proceedings of the 35th IEEE VLSI Test Symposium, 2017

RTL functional test generation using factored concolic execution.

[BibT_eX]

[DOI]

Sonal Pinto

Proceedings of the IEEE International Test Conference, 2017

Fast Search-Based RTL Test Generation Using Control-Flow Path Guidance.

[BibT_eX]

[DOI]

Sonal Pinto

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

A Test Pattern Quality Metric for Diagnosis of Multiple Stuck-at and Transition faults.

[BibT_eX]

[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016

A control path aware metric for grading functional test vectors.

[BibT_eX]

[DOI]

Proceedings of the 17th Latin-American Test Symposium, 2016

Fast Multi-level Test Generation at the RTL.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Hardware-in-the-loop model-less diagnostic test generation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2016

Dynamic partitioning strategy to enhance symbolic execution.

[BibT_eX]

[DOI]

Brendan A. Marcellino

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

Abstraction-based relation mining for functional test generation.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Information-theoretic and statistical methods of failure log selection for improved diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Test Conference, 2015

Fast Stimuli Generation for Design Validation of RTL Circuits Using Binary Particle Swarm Optimization.

[BibT_eX]

[DOI]

Prateek Puri

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Novel SAT-based invariant-directed low-power synthesis.

[BibT_eX]

[DOI]

Mustafa ElNainay

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Signal domain based reachability analysis in RTL circuits.

[BibT_eX]

[DOI]

Sharad Bagri

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

SI-SMART: Functional test generation for RTL circuits using loop abstraction and learning recurrence relationships.

[BibT_eX]

[DOI]

Prateek Puri

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Branch guided functional test generation at the RTL.

[BibT_eX]

[DOI]

Vineeth V. Acharya

Sharad Bagri

Proceedings of the 20th IEEE European Test Symposium, 2015

2014

Hardware Trojan Attacks: Threat Analysis and Countermeasures.

[BibT_eX]

[DOI]

Proc. IEEE, 2014

A diagnosis-friendly LBIST architecture with property checking.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Test Conference, 2014

Property-checking based LBIST for improved diagnosability.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE European Test Symposium, 2014

GPU-based timing-aware test generation for small delay defects.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE European Test Symposium, 2014

TACUE: A Timing-Aware Cuts Enumeration Algorithm for Parallel Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Dual-Purpose Mixed-Level Test Generation Using Swarm Intelligence.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

Protection Against Hardware Trojan Attacks: Towards a Comprehensive Solution.

[BibT_eX]

[DOI]

IEEE Des. Test, 2013

POCKET: A tool for protecting children's privacy online.

[BibT_eX]

[DOI]

Decis. Support Syst., 2013

Selecting critical implications with set-covering formulation for SAT-based Bounded Model Checking.

[BibT_eX]

[DOI]

Mustafa Y. ElNainay

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

A novel statistical and circuit-based technique for counterfeit detection in existing ICs.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Set-cover-based critical implications selection to improvesat-based bounded model checking: extended abstract.

[BibT_eX]

[DOI]

Mustafa Y. ElNainay

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Test generation for circuits with embedded memories using SMT.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE European Test Symposium, 2013

A novel concurrent cache-friendly binary decision diagram construction for multi-core platforms.

[BibT_eX]

[DOI]

Mustafa Y. ElNainay

Proceedings of the Design, Automation and Test in Europe, 2013

LFSR seed computation and reduction using SMT-based fault-chaining.

[BibT_eX]

[DOI]

Dhrumeel Bakshi

Proceedings of the Design, Automation and Test in Europe, 2013

Interlocking obfuscation for anti-tamper hardware.

[BibT_eX]

[DOI]

Proceedings of the Cyber Security and Information Intelligence, 2013

Functional Test Generation at the RTL Using Swarm Intelligence and Bounded Model Checking.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asian Test Symposium, 2013

2012

Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2012

Reducing descriptor measurement error through Bayesian estimation of fingerprint minutia location and direction.

[BibT_eX]

[DOI]

IET Biom., 2012

A SMT-based diagnostic test generation method for combinational circuits.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE VLSI Test Symposium, 2012

A Novel SMT-Based Technique for LFSR Reseeding.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on VLSI Design, 2012

Design validation of RTL circuits using evolutionary swarm intelligence.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Test Conference, 2012

Sequential equivalence checking of hard instances with targeted inductive invariants and efficient filtering strategies.

[BibT_eX]

[DOI]

Huy Nguyen

Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

RAG: An efficient reliability analysis of logic circuits on graphics processing units.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A scan pattern debugger for partial scan industrial designs.

[BibT_eX]

[DOI]

Supratik K. Misra

Sanjay Sengupta

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Temporal analysis of fingerprint impressions.

[BibT_eX]

[DOI]

Proceedings of the IEEE Fifth International Conference on Biometrics: Theory, 2012

Robust feature extraction in fingerprint images using ridge model tracking.

[BibT_eX]

[DOI]

Proceedings of the IEEE Fifth International Conference on Biometrics: Theory, 2012

2011

Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

3-D Parallel Fault Simulation With GPGPU.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Strategies for scalable symbolic execution-driven test generation for programs.

[BibT_eX]

[DOI]

Saparya Krishnamoorthy

Sci. China Inf. Sci., 2011

Trace Buffer-Based Silicon Debug with Lossless Compression.

[BibT_eX]

[DOI]

Sandesh Prabhakar

Rajamani Sethuram

Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Fault Collapsing Using a Novel Extensibility Relation.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

A Novel Learning Framework for State Space Exploration Based on Search State Extensibility Relation.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Latent fingerprint segmentation using ridge template correlation.

[BibT_eX]

[DOI]

Proceedings of the 4th International Conference on Imaging for Crime Detection and Prevention, 2011

Minutiae + friction ridges = triplet-based features for determining sufficiency in fingerprints.

[BibT_eX]

[DOI]

Proceedings of the 4th International Conference on Imaging for Crime Detection and Prevention, 2011

A Bayesian approach to fingerprint minutia localization and quality assessment using adaptable templates.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Joint Conference on Biometrics, 2011

ODETTE: A non-scan design-for-test methodology for Trojan detection in ICs.

[BibT_eX]

[DOI]

Proceedings of the HOST 2011, 2011

Utilizing GPGPUs for design validation with a modified Ant Colony Optimization.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011

Sufficiency-based filtering of invariants for Sequential Equivalence Checking.

[BibT_eX]

[DOI]

Wei Hu

Huy Nguyen

Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011

High-Performance Diagnostic Fault Simulation on GPUs.

[BibT_eX]

[DOI]

Proceedings of the 16th European Test Symposium, 2011

Experiment and Analysis Services in a Fingerprint Digital Library for Collaborative Research.

[BibT_eX]

[DOI]

Proceedings of the Research and Advanced Technology for Digital Libraries, 2011

Design-for-test methodology for non-scan at-speed testing.

[BibT_eX]

[DOI]

Nikhil P. Rahagude

Proceedings of the Design, Automation and Test in Europe, 2011

An Efficient 2-Phase Strategy to Achieve High Branch Coverage.

[BibT_eX]

[DOI]

Sarvesh Prabhu

Saparya Krishnamoorthy

Vijay Gangaram

Jim Grundy

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

Search State Compatibility Based Incremental Learning Framework and Output Deviation Based X-filling for Diagnostic Test Generation.

[BibT_eX]

[DOI]

Nikhil P. Rahagude

J. Electron. Test., 2010

Multiplexed trace signal selection using non-trivial implication-based correlation.

[BibT_eX]

[DOI]

Sandesh Prabhakar

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Trusted RTL: Trojan Detection Methodology in Pre-silicon Designs.

[BibT_eX]

[DOI]

Proceedings of the HOST 2010, 2010

Reversible logic synthesis through ant colony optimization.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

DFT + DFD: An Integrated Method for Design for Testability and Diagnosability.

[BibT_eX]

[DOI]

Nikhil P. Rahagude

Proceedings of the 19th IEEE Asian Test Symposium, 2010

FSimGP^2: An Efficient Fault Simulator with GPGPU.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Asian Test Symposium, 2010

Tackling the Path Explosion Problem in Symbolic Execution-Driven Test Generation for Programs.

[BibT_eX]

[DOI]

Saparya Krishnamoorthy

Claudio R. C. M. da Silva

Proceedings of the 19th IEEE Asian Test Symposium, 2010

Mining Complex Boolean Expressions for Sequential Equivalence Checking.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009

Cognitive Radio and Networking Research at Virginia Tech.

[BibT_eX]

[DOI]

Proc. IEEE, 2009

A Novel Sustained Vector Technique for the Detection of Hardware Trojans.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Evaluation of Online Resources in Assisting Phishing Detection.

[BibT_eX]

[DOI]

Proceedings of the Ninth Annual International Symposium on Applications and the Internet, 2009

An ant colony optimization technique for abstraction-guided state justification.

[BibT_eX]

[DOI]

Proceedings of the 2009 IEEE International Test Conference, 2009

Fast circuit topology based method to configure the scan chains in Illinois Scan architecture.

[BibT_eX]

[DOI]

Swapneel Donglikar

Proceedings of the 2009 IEEE International Test Conference, 2009

VITAMIN: Voltage Inversion Technique to Ascertain Malicious Insertions in ICs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2009

Diagnostic Test Generation for silicon diagnosis with an incremental learning framework based on search state compatibility.

[BibT_eX]

[DOI]

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009

An efficient path-oriented bitvector encoding width computation algorithm for bit-precise verification.

[BibT_eX]

[DOI]

Nannan He

Proceedings of the Design, Automation and Test in Europe, 2009

Using Non-trivial Logic Implications for Trace Buffer-Based Silicon Debug.

[BibT_eX]

[DOI]

Sandesh Prabhakar

Proceedings of the Eighteentgh Asian Test Symposium, 2009

Kiss the Scan Goodbye: A Non-scan Architecture for High Coverage, Low Test Data Volume and Low Test Application Time.

[BibT_eX]

[DOI]

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

Introduction to special section on high-level design, validation, and test.

[BibT_eX]

[DOI]

Robert B. Jones

ACM Trans. Design Autom. Electr. Syst., 2008

Mining Global Constraints With Domain Knowledge for Improving Bounded Sequential Equivalence Checking.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Boosting SAT Solver Performance via a New Hybrid Approach.

[BibT_eX]

[DOI]

J. Satisf. Boolean Model. Comput., 2008

A New Scan Architecture for Both Low Power Testing and Test Volume Compression Under SOC Test Environment.

[BibT_eX]

[DOI]

Hong-Sik Kim

Sungho Kang

J. Electron. Test., 2008

Bilateral Testing of Nano-scale Fault-Tolerant Circuits.

[BibT_eX]

[DOI]

J. Electron. Test., 2008

SAT-based State Justification with Adaptive Mining of Invariants.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

Quantifying the energy efficiency of coordinated micro-architectural adaptation for multimedia workloads.

[BibT_eX]

[DOI]

Shrirang M. Yardi

Proceedings of the 26th International Conference on Computer Design, 2008

Ant Colony Optimization directed program abstraction for software bounded model checking.

[BibT_eX]

[DOI]

Xueqi Cheng

Proceedings of the 26th International Conference on Computer Design, 2008

A Region Based Approach for the Identification of Hardware Trojans.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2008

On dynamic switching of navigation for semi-formal design validation.

[BibT_eX]

[DOI]

Ankur Parikh

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

SAT-based equivalence checking of threshold logic designs for nanotechnologies.

[BibT_eX]

[DOI]

Yexin Zheng

Chao Huang

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Guided test generation for isolation and detection of embedded trojans in ics.

[BibT_eX]

[DOI]

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Efficient Design Validation Based on Cultural Algorithms.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

A Fast Approximation Algorithm for MIN-ONE SAT.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Simulation-Directed Invariant Mining for Software Verification.

[BibT_eX]

[DOI]

Xueqi Cheng

Proceedings of the Design, Automation and Test in Europe, 2008

On Providing Automatic Parental Consent over Information Collection from Children.

[BibT_eX]

Karthik Channakeshava

Proceedings of the 2008 International Conference on Security & Management, 2008

2007

An Overlapping Scan Architecture for Reducing Both Test Time and Test Power by Pipelining Fault Detection.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

Using Scan-Dump Values to Improve Functional-Diagnosis Methodology.

[BibT_eX]

[DOI]

M. Enamul Amyeen

Ruifeng Guo

Srikanth Venkataraman

Kai Yang

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Explicit Safety Property Strengthening in SAT-based Induction.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Integrating Validation and Verification in the Digital Design Curriculum.

[BibT_eX]

[DOI]

Shrirang M. Yardi

Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

Mining-guided state justification with partitioned navigation tracks.

[BibT_eX]

[DOI]

Ankur Parikh

Proceedings of the 2007 IEEE International Test Conference, 2007

Efficient power droop aware delay fault testing.

[BibT_eX]

[DOI]

Bin Li

Proceedings of the 2007 IEEE International Test Conference, 2007

Bounded model checking of embedded software in wireless cognitive radio systems.

[BibT_eX]

[DOI]

Nannan He

Proceedings of the 25th International Conference on Computer Design, 2007

A new hybrid solution to boost SAT solver performance.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Mining Sequential Constraints for Pseudo-Functional Testing.

[BibT_eX]

[DOI]

Proceedings of the 16th Asian Test Symposium, 2007

Parents and the Internet: Privacy Awareness, Practices and Control.

[BibT_eX]

[DOI]

Karthik Channakeshava

Kaigui Bian

Jung-Min Park

Proceedings of the Reaching New Heights. 13th Americas Conference on Information Systems, 2007

2006

A Framework for Automatic Design Validation of RTL Circuits Using ATPG and Observability-Enhanced Tag Coverage.

[BibT_eX]

[DOI]

Indradeep Ghosh

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

State Variable Extraction and Partitioning to Reduce Problem Complexity for ATPG and Design Validation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

New techniques for untestable fault identification in sequential circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

A New Simulation-Based Property Checking Algorithm Based on Partitioned Alternative Search Space Traversal.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2006

Testing Embedded Sequential Cores in Parallel Using Spectrum-Based BIST.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2006

Efficient Fault Collapsing via Generalized Dominance Relations.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

A Study of Implication Based Pseudo Functional Testing.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Test Conference, 2006

Characteristic States and Cooperative Game Based Search for Efficient Sequential ATPG and Design Validation.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Test Conference, 2006

Implicit Search-Space Aware Cofactor Expansion: A Novel Preimage Computation Technique.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Mining global constraints for improving bounded sequential equivalence checking.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

Fast illegal state identification for improving SAT-based induction.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

2005

Efficient techniques for transition testing.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2005

Error Diagnosis of Sequential Circuits Using Region-Based Model.

[BibT_eX]

[DOI]

Anand L. D'Souza

J. Electron. Test., 2005

A Novel Transition Fault ATPG That Reduces Yield Loss.

[BibT_eX]

[DOI]

Xiao Liu

IEEE Des. Test Comput., 2005

Q-PREZ: QBF Evaluation Using Partition, Resolution and Elimination with ZBDDs.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Towards an Intrusion Detection System for Battery Exhaustion Attacks on Mobile Computing Devices.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE Conference on Pervasive Computing and Communications Workshops (PerCom 2005 Workshops), 2005

Region-level approximate computation reuse for power reduction in multimedia applications.

[BibT_eX]

[DOI]

Xueqi Cheng

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

A Formal Framework for Modeling and Analysis of System-Level Dynamic Power Management.

[BibT_eX]

[DOI]

Shrirang M. Yardi

Karthik Channakeshava

Thomas L. Martin

Dong S. Ha

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Extended Forward Implications and Dual Recurrence Relations to Identify Sequentially Untestable Faults.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

State Set Management for SAT-based Unbounded Model Checking.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Increasing the deducibility in CNF instances for efficient SAT-based bounded model checking.

[BibT_eX]

[DOI]

Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005

VERISEC: verifying equivalence of sequential circuits using SAT.

[BibT_eX]

[DOI]

Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005

Untestable fault identification through enhanced necessary value assignments.

[BibT_eX]

[DOI]

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

An effective and efficient ATPG-based combinational equivalence checker.

[BibT_eX]

[DOI]

Ronald P. Lajaunie

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Forward image computation with backtracing ATPG and incremental state-set construction.

[BibT_eX]

[DOI]

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Quality-Driven Proactive Computation Elimination for Power-Aware Multimedia Processing.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Integration of Learning Techniques into Incremental Satisfiability for Efficient Path-Delay Fault Test Generation.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Dynamic abstraction using SAT-based BMC.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

Interleaved Invariant Checking with Dynamic Abstraction.

[BibT_eX]

[DOI]

Proceedings of the Correct Hardware Design and Verification Methods, 2005

Untestable Multi-Cycle Path Delay Faults in Industrial Designs.

[BibT_eX]

[DOI]

Suriyaprakash Natarajan

Sreejit Chakravarty

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

Using Global Structural Relationships of Signals to Accelerate SAT-based Combinational Equivalence Checking.

[BibT_eX]

[DOI]

J. Univers. Comput. Sci., 2004

Success-Driven Learning in ATPG for Preimage Computation.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2004

Efficient ATPG for Design Validation Based On Partitioned State Exploration Histories.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Untestable Fault Identification using Recurrence Relations and Impossible Value Assignments.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Can SAT be used to Improve Sequential ATPG Methods?

[BibT_eX]

[DOI]

Jawahar Jain

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Enhancing SAT-based Bounded Model Checking using Sequential Logic Implications.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Denial-of-Service Attacks on Battery-powered Mobile Computers.

[BibT_eX]

[DOI]

Proceedings of the Second IEEE International Conference on Pervasive Computing and Communications (PerCom 2004), 2004

State Variable Extraction to Reduce Problem Complexity for ATPG and Design Validation.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Identifying Untestable Transition Faults in Latch Based Designs with Multiple Clocks.

[BibT_eX]

[DOI]

Sreejit Chakravarty

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

ALAPTF: A new Transition Faultmodel and the ATPG Algorithm.

[BibT_eX]

[DOI]

Puneet Gupta

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Decision Selection and Learning for an All-Solutions ATPG Engine.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Incremental deductive & inductive reasoning for SAT-based bounded model checking.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

On identifying functionally untestable transition faults.

[BibT_eX]

[DOI]

Xiao Liu

Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

CNF formula simplification using implication reasoning.

[BibT_eX]

[DOI]

Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

A Novel SAT All-Solutions Solver for Efficient Preimage Computation.

[BibT_eX]

[DOI]

Bin Li

Proceedings of the 2004 Design, 2004

2003

Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors.

[BibT_eX]

[DOI]

J. Electron. Test., 2003

Efficient Implication - Based Untestable Bridge Fault Identifier.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Energy-Efficient Logic BIST Based on State Correlation Analysis.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Efficient Sequential ATPG for Functional RTL Circuits.

[BibT_eX]

[DOI]

Indradeep Ghosh

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Efficient Sequential ATPG Based on Partitioned Finite-State-Machine Traversal.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

High Quality ATPG for Delay Defects.

[BibT_eX]

[DOI]

Puneet Gupta

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

ATPG-based preimage computation: efficient search space pruning with ZBDD.

[BibT_eX]

[DOI]

Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

Enhancing SAT-based equivalence checking with static logic implications.

[BibT_eX]

[DOI]

Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

Constrained ATPG for Broadside Transition Testing.

[BibT_eX]

[DOI]

Xiao Liu

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

A Novel, Low-Cost Algorithm for Sequentially Untestable Fault Identification.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

Efficient Preimage Computation Using A Novel Success-Driven ATPG.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

Automatic Design Validation Framework for HDL Descriptions via RTL ATPG.

[BibT_eX]

[DOI]

Indradeep Ghosh

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

Genetic Spot Optimization for Peak Power Estimation in Large VLSI Circuits.

[BibT_eX]

[DOI]

VLSI Design, 2002

Behavioral-Level DFT via Formal Operator Testability Measures.

[BibT_eX]

[DOI]

J. Electron. Test., 2002

State and Fault Information for Compaction-Based Test Generation.

[BibT_eX]

[DOI]

J. Electron. Test., 2002

Efficient Sequential Test Generation Based on Logic Simulation.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2002

Spectrum-Based BIST in Complex SOCs.

[BibT_eX]

[DOI]

Ganapathy Kasturirangan

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

A Hardware Architecture for Dynamic Performance and Energy Adaptation.

[BibT_eX]

[DOI]

Phillip Stanley-Marbell

Ulrich Kremer

Proceedings of the Power-Aware Computer Systems, Second International Workshop, 2002

Reducing Power Consumption by Utilizing Retransmission in Short Range Wireless Network.

[BibT_eX]

[DOI]

Yufeng Zhao

Proceedings of the 27th Annual IEEE Conference on Local Computer Networks (LCN 2002), 2002

Improving Sequential ATPG Using SAT Methods.

[BibT_eX]

Jawahar Jain

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Techniques to Reduce Data Volume and Application Time for Transition Test.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Characteristic faults and spectral information for logic BIST.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Novel ATPG algorithms for transition faults.

[BibT_eX]

[DOI]

Proceedings of the 7th European Test Workshop, 2002

Maximizing Impossibilities for Untestable Fault Identification.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

Effective safety property checking using simulation-based sequential ATPG.

[BibT_eX]

[DOI]

Koichiro Takayama

Proceedings of the 39th Design Automation Conference, 2002

2001

Exploring the Interaction between Java?s Implicitly Thrown Exceptions and Instruction Scheduling.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 2001

Novel Spectral Methods for Built-In Self-Test in a System-on-a-Chip Environment.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Combination of Structural and State Analysis for Partial Scan.

[BibT_eX]

[DOI]

Sameer Sharma

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Accurate Power Macro-modeling Techniques for Complex RTL Circuits.

[BibT_eX]

[DOI]

Nachiketh R. Potlapally

Anand Raghunathan

Ganesh Lakshminarayana

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Error Diagnosis of Sequential Circuits Using Region-Based Mode.

[BibT_eX]

[DOI]

Anand L. D'Souza

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

On efficient error diagnosis of digital circuits.

[BibT_eX]

[DOI]

Nandini Sridhar

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Fast, flexible, cycle-accurate energy estimation.

[BibT_eX]

[DOI]

Phillip Stanley-Marbell

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Compiler-directed dynamic voltage/frequency scheduling for energy reduction in mircoprocessors.

[BibT_eX]

[DOI]

Chung-Hsing Hsu

Ulrich Kremer

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Practical use of sequential ATPG for model checking: going the extra mile does pay off.

[BibT_eX]

[DOI]

Jawahar Jain

Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

Efficient spectral techniques for sequential ATPG.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

Peak power estimation of VLSI circuits: new peak power measures.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2000

Dynamic state traversal for sequential circuit test generation.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2000

Formal Value-Range and Variable Testability Techniques for High-Level Design-For-Testability.

[BibT_eX]

[DOI]

J. Electron. Test., 2000

Test Set and Fault Partitioning Techniques for Static Test Sequence Compaction for Sequential Circuits.

[BibT_eX]

[DOI]

J. Electron. Test., 2000

Test Set Compaction Using Relaxed Subsequence Removal.

[BibT_eX]

[DOI]

J. Electron. Test., 2000

Testing, Verification, and Diagnosis in the Presence of Unknowns.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Compiler-Directed Dynamic Frequency and Voltage Scheduling.

[BibT_eX]

[DOI]

Chung-Hsing Hsu

Ulrich Kremer

Proceedings of the Power-Aware Computer Systems, First International Workshop, 2000

Formal operator testability methods for behavioral-level DFT using value ranges.

[BibT_eX]

[DOI]

Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000

Multi-Node Static Logic Implications for Redundancy Identification.

[BibT_eX]

[DOI]

Kabir Gulrajani

Proceedings of the 2000 Design, 2000

Embedded core testing using genetic algorithms.

[BibT_eX]

[DOI]

Ruofan Xu

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

Compaction-based test generation using state and fault information.

[BibT_eX]

[DOI]

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

Fast Static Compaction Algorithms for Sequential Circuit Test Vectors.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1999

On Non-Statistical Techniques for Fast Fault Coverage Estimation.

[BibT_eX]

[DOI]

J. Electron. Test., 1999

Partial Scan Using Multi-Hop State Reachability Analysis.

[BibT_eX]

[DOI]

Sameer Sharma

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

On the Evaluation of Arbitrary Defect Coverage of Test Sets.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Instruction Scheduling in the Presence of Java's Runtime Exceptions.

[BibT_eX]

[DOI]

Proceedings of the Languages and Compilers for Parallel Computing, 1999

An integrated approach to behavioral-level design-for-testability using value-range and variable testability techniques.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Peak Power Estimation Using Genetic Spot Optimization for Large VLSI Circuits.

[BibT_eX]

[DOI]

Proceedings of the 1999 Design, 1999

1998

Application of genetically engineered finite-state-machine sequences to sequential circuit ATPG.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Partial Scan Selection Based on Dynamic Reachability and Observability Information.

[BibT_eX]

[DOI]

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

A fast, accurate, and non-statistical method for fault coverage estimation.

[BibT_eX]

[DOI]

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential Circuits.

[BibT_eX]

[DOI]

Proceedings of the 1998 Design, 1998

Partitioning and Reordering Techniques for Static Test Sequence Compaction of Sequential Circuits.

[BibT_eX]

[DOI]

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997

Sequential Circuit Test Generation Using Genetic Techniques

[BibT_eX]

[DOI]

PhD thesis, 1997

Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

K2: an estimator for peak sustainable power of VLSI circuits.

[BibT_eX]

[DOI]

Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Effects of delay models on peak power estimation of VLSI sequential circuits.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Partial Scan beyond Cycle Cutting.

[BibT_eX]

[DOI]

Gurjeet S. Saund

Proceedings of the Digest of Papers: FTCS-27, 1997

Sequential circuit test generation using dynamic state traversal.

[BibT_eX]

[DOI]

Proceedings of the European Design and Test Conference, 1997

1996

Automatic test generation using genetically-engineered distinguishing sequences.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Alternating Strategies for Sequential Circuit ATPG.

[BibT_eX]

[DOI]

Proceedings of the 1996 European Design and Test Conference, 1996

1995

A new architectural-level fault simulation using propagation prediction of grouped fault-effects.

[BibT_eX]

[DOI]