Michael Pietzko

Orcid: 0000-0003-2369-5522

According to our database1, Michael Pietzko authored at least 10 papers between 2021 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
A 600MS/s 10-bit SAR ADC with unit via-based delta-length C-DAC in 22nm FDSOI.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Using Negative-R Assisted Integrators in Wide-band Delta-Sigma Modulators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
Delay Error Shaping in ΔΣ Modulators Using Time-Interleaved High Resolution Quantizers.
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023

Bitwise ELD Compensation under Integrator Nonidealities in ΔΣ Modulators.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

A Chopped 6-bit 1.6 GS/s SAR ADC Utilizing Slow Decision Information in 22 nm FDSOI.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2022
Maximizing the Inter-Stage Gain in CT 0-X MASH Delta-Sigma-Modulators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Bitwise ELD Compensation in Δ∑ Modulators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
A direct-digitization open-loop gyroscope frontend with +/-8000°/s full-scale range and noise floor of 0.0047°/s/√Hz.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

Influence of Excess Loop Delay on the STF of Continuous-Time Delta-Sigma Modulators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

FIR Filter with Symmetric Non-Equal Coefficients for CT Delta-Sigma Modulators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021


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