Michael Peter Kennedy

Orcid: 0000-0003-3242-1056

Affiliations:
  • University College Cork, Ireland


According to our database1, Michael Peter Kennedy authored at least 160 papers between 1991 and 2024.

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Bibliography

2024
10.4 A 45.5fs-Integrated-Random-Jitter and -75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional, Horn, and Wandering Spurs.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

Comparison of DTC Segmentation Methods in Fractional-N Frequency Synthesizers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
Enhanced Jitter Analysis and Minimization for Digital PLLs With Mid-Rise TDCs and its Impact on Output Phase Noise.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

Optimized MASH-SR Divider Controller for Fractional-N Frequency Synthesizers.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2023

Performance Limits of Fractional-N Digital PLLs with Mid-Rise TDCs.
Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023

MMSE Estimator for Linearized Analysis and SNR of ADCs Tested with Sinusoidal Inputs.
Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023

Linearized Analysis of Mid-Rise TDCs for Integer-N and Fractional-N Digital PLLs.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Comparative Study of Linearized Analysis Frameworks for Mid-Rise TDCs.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Initial Condition-Dependent Spur Pattern Induced by Undithered MASH DDSM Divider Controller.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Comparison of DTC-Related Spurs in Fractional-N Digital PLLs with MASH-and-ENOP-based Divider Controllers.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

Further Insights into Spur Immunity in MASH-Based Fractional-N CP-PLLs with Polynomial Nonlinearities.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

2022
Nonlinearity-Induced Spurs in Fractional-N Frequency Synthesizers.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Family of ΔΣ Modulators With High Spur Immunity and Low Folded Nonlinearity Noise When Used in Fractional- Frequency Synthesizers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Wandering Spur Suppression in a 4.9-GHz Fractional-N Frequency Synthesizer.
IEEE J. Solid State Circuits, 2022

A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping.
IEEE J. Solid State Circuits, 2022

A random pulse modulation approach to modeling the flicker and white noise of the charge pump of a fractional-N frequency synthesizer.
Int. J. Circuit Theory Appl., 2022

Immunity of ENOP-based Fractional-N Frequency Synthesizer to Wandering and Horn Spurs.
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022

Wandering Spurs in MASH-Based Fractional-N Frequency Synthesizers - How They Arise and How to Get Rid of Them
Springer, ISBN: 978-3-030-91284-0, 2022

2021
Folded Noise Prediction in Nonlinear Fractional-N Frequency Synthesizers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Spur Immunity in MASH-Based Fractional-N CP-PLLs With Polynomial Nonlinearities.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

MASH-Based Divider Controllers for Mitigation of Wandering Spurs in a Fractional-N Frequency Synthesizer.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

An Algorithm for Implementing a Modulator Whose Output is Spur-Free After Nonlinear Distortion.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

Experimental Verification of Wandering Spur Suppression Technique in a 4.9 GHz Fractional-N Frequency Synthesizer.
Proceedings of the 47th ESSCIRC 2021, 2021

2020
Modelling and Verification of Nonlinear Electromechanical Coupling in Micro-Scale Kinetic Electromagnetic Energy Harvesters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Mitigation of "Horn Spurs" in a MASH-Based Fractional-N CP-PLL.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Influence of Initial Condition on Wandering Spur Pattern in a MASH-Based Fractional-N Frequency Synthesizer.
IEEE Trans. Circuits Syst., 2020

Analysis of Wandering Spur Patterns in a Fractional-N Frequency Synthesizer With a MASH-Based Divider Controller.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Jitter Minimization in Digital PLLs with Mid-Rise TDCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Near-Limit Kinetic Energy Harvesting From Arbitrary Acceleration Waveforms: Feasibility Study by the Example of Human Motion.
IEEE Access, 2020

A Curious Result concerning Spur Generation in MASH 1-1-1 based Fractional-N CP-PLLs with a Second-Order Nonlinearity.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

2019
Prediction of Phase Noise and Spurs in a Nonlinear Fractional-N Frequency Synthesizer.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Wandering Spurs in MASH 1-1 Delta-Sigma Modulators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

4.48GHz 0.18μm SiGe BiCMOS Exact-Frequency Fractional-N Frequency Synthesizer with Spurious-Tone Suppression Yielding a -80dBc In-Band Fractional Spur.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Method of Equivalent Currents for the Calculation of Magnetic Fields in Inductors and Magnets with Application to Electronics.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Observations concerning "Horn Spurs" in a MASH-based Fractional-N CP-PLL.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

MASH DDSM-Induced Spurs in a Fractional-N Frequency Synthesizer.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Nonlinearity-Induced Spurs in Fractional-N Frequency Synthesizers: State of the Art.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

An Eight-Phase 40GHz RTWO in 28nm CMOS with Phase Noise Reduction Via Head and Tail Filtering.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

2018
Observations and Analysis of Wandering Spurs in MASH-Based Fractional-N Frequency Synthesizers.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A Design Method for Nested MASH-SQ Hybrid Divider Controllers for Fractional-N Frequency Synthesizers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

High-Speed Nested Cascaded MASH Digital Delta-Sigma Modulator-Based Divider Controller.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Novel Approach to Modelling Electromechanical Coupling and Testing its Self-Consistency in Micro-Scale Kinetic Electromagnetic Energy Harvesters.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
Masked Dithering of MASH Digital Delta-Sigma Modulators With Constant Inputs Using Multiple Linear Feedback Shift Registers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Influence of Initial Conditions on the Fundamental Periods of LFSR-Dithered MASH Digital Delta-Sigma Modulators With Constant Inputs.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Nonlinearity-induced spurious tones and noise in digitally-assisted frequency synthesizers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
Masked Dithering of MASH Digital Delta-Sigma Modulators with Constant Inputs Using Linear Feedback Shift Registers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Comparison of analytical predictions of the noise floor due to static charge pump mismatch in fractional-n frequency synthesizers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Comparative analysis of differential colpitts and cross-coupled VCOs in 180 nm Si-Ge HBT technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A method to quantify the dependence of spur heights on offset current in a CP-PLL.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Maximizing the fundamental period of a dithered digital delta-sigma modulator with constant input.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Yet another spur mechanism in a charge-pump based Fractional-N PLL.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Comments on "folding of phase noise spectra in charge-pump phase-locked loops induced by frequency division".
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

On the statistical properties of phase noise in Fractional-N frequency synthesizers using successive requantizers.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015
Spurious tones in digital delta-sigma modulators resulting from pseudorandom dither.
J. Frankl. Inst., 2015

The noise and spur delusion in fractional-N frequency synthesizer design.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Effective (Spur-Free) dithering of digital delta-sigma modulators with pseudorandom dither.
Proceedings of the European Conference on Circuit Theory and Design, 2015

2014
0.3-4.3 GHz Frequency-Accurate Fractional-N Frequency Synthesizer With Integrated VCO and Nested Mixed-Radix Digital Δ-Σ Modulator-Based Divider Controller.
IEEE J. Solid State Circuits, 2014

Comments on efficient dithering in digital delta-sigma modulator.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013
The Role of Charge Pump Mismatch in the Generation of Integer Boundary Spurs in Fractional-N Frequency Synthesizers: Why Worse Can Be Better.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

A CMOS Injection-Locked Frequency Divider Optimized for Divide-by-Two and Divide-by-Three Operation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Spurious tones in digital delta sigma modulators with pseudorandom dither.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

High speed, high accuracy fractional-N frequency synthesizer using nested mixed-radix digital Δ-Σ modulators.
Proceedings of the ESSCIRC 2013, 2013

Experimental validation of DAC with nested bus-splitting EFM4 DDSM.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

A high-throughput spur-free hybrid nested bus-splitting/HK-MASH digital delta-sigma modulator.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

Implementation of a pulse-holding Time-to-Digital Converter on an FPGA.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

An LC CMOS injection-locked frequency divider for divide-by-two and divide-by-three operation.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

2012
Hardware Reduction in Digital Delta-Sigma Modulators via Bus-Splitting and Error Masking - Part II: Non-Constant Input.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A fast charge pump PLL using a bang-bang frequency comparator with dead zone.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A "divide-by-odd number" direct injection CMOS LC injection-locked frequency divider.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
Observations Concerning the Generation of Spurious Tones in Digital Delta-Sigma Modulators Followed by a Memoryless Nonlinearity.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

A Spur-Free MASH DDSM With High-Order Filtered Dither.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

Hardware Reduction in Digital Delta-Sigma Modulators Via Bus-Splitting and Error Masking - Part I: Constant Input.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Calculation of Cycle Lengths in Higher Order Error Feedback Modulators With Constant Inputs.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

Observations Concerning the Locking Range in a Complementary Differential LC Injection-Locked Frequency Divider - Part II: Design Methodology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

On the Synchronization Condition for Superharmonic Coupled QVCOs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

A novel implementation of dithered digital delta-sigma modulators via bus-splitting.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

First order noise shaping in all digital PLLs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Experimental characterization of Arnold tongues in injection-locked CMOS LC frequency dividers with tail and direct injection.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

Phenomenological study of an injection-locked CMOS LC frequency divider with direct injection.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010
Analysis and Design of Injection-Locked Frequency Dividers by Means of a Phase-Domain Macromodel.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Prediction of the Spectrum of a Digital Delta-Sigma Modulator Followed by a Polynomial Nonlinearity.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Observations Concerning the Locking Range in a Complementary Differential LC Injection-Locked Frequency Divider - Part I: Qualitative Analysis.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Estimating the locking range of analog dividers through a phase-domain macromodel.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Calculation of the cycle length in a HK-MASH DDSM with multilevel quantizers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A qualitative analysis of a complementary differential LC injection-locked frequency divider based on direct injection.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

On the synchronization condition of second-harmonic coupled QVCOs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Calculation of cycle lengths in higher-order MASH DDSMs with constant inputs.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

First Order Noise Shaping Local-Oscillator Based Time-to-Digital Converter.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009
Hardware Reduction in Digital Delta-Sigma Modulators Via Error Masking - Part II: SQ-DDSM.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

Hardware Reduction in Digital Delta-Sigma Modulators Via Error Masking - Part I: MASH DDSM.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Calculation of cycle lengths in MASH 1-2-2 digital delta sigma modulators with a constant input.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

A spur-free MASH digital delta-sigma modulator with higher order shaped dither.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2008
Architectures for Maximum-Sequence-Length Digital Delta-Sigma Modulators.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

Statistical Properties of First-Order Bang-Bang PLL With Nonzero Loop Delay.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

Design methodology for a dithered reduced complexity Digital MASH Delta-Sigma Modulator.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Design methodology for a divide-by-4 LC injection-locked frequency divider based on nonlinear analysis.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
Reduced Complexity MASH Delta-Sigma Modulator.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

Mathematical Analysis of a Prime Modulus Quantizer MASH Digital Delta-Sigma Modulator.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

Maximum Sequence Length MASH Digital Delta-Sigma Modulators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Modeling and Simulation of Delta-Sigma Fractional-<i>N</i> PLL Frequency Synthesizer in Verilog-AMS.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Hard-Fault Detection and Diagnosis During the Application of Model-Based Data Converter Testing.
J. Electron. Test., 2007

A novel dual-loop multi-phase frequency synthesizer.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

Optimizing the design of an injection-locked frequency divider by means of nonlinear analysis.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006
Test Development Through Defect and Test Escape Level Estimation for Data Converters.
J. Electron. Test., 2006

Locking range analysis for injection-locked frequency dividers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

The optimum power conversion efficiency and associated gain of an LC CMOS oscillator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Use of the Step Invariant Transform to Design a 2nd Order Continuous Time Complex Sigma-Delta ADC.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
Influence of noise intensity on the spectrum of an oscillator.
IEEE Trans. Circuits Syst. II Express Briefs, 2005

A Fast and Simple Implementation of Chua's oscillator with cubic-like Nonlinearity.
Int. J. Bifurc. Chaos, 2005

On the Approximate One-d Map in Chua's oscillator.
Int. J. Bifurc. Chaos, 2005

Overcoming Test Setup Limitations by Applying Model-Based Testing to High-Precision ADCs.
J. Electron. Test., 2005

Innovation to overcome limitations of test equipment.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

Comments on the effectiveness of the Szabo and Kolumban solution to false lock in sampling PLL frequency synthesizer.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

Accurate modeling and experimental validation of an injection-locked frequency divider.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

The Devil's Staircase as a method of comparing injection-locked frequency divider topologies.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

A fast and simple implementation of Chua's oscillator using a "cubic-like" Chua diode.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

Influence of a "coupling factor" on the spectrum of a noisy oscillator.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

Observations on the relationship between energy transfer efficiency and phase noise in an LC oscillator.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

2004
Linear model-based testing of ADC nonlinearities.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A general method to predict the amplitude of oscillation in nearly sinusoidal oscillators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Testing ADCs for static and dynamic INL - killing two birds with one stone.
Comput. Stand. Interfaces, 2004

A technique to reduce flicker noise up-conversion in CMOS LC voltage-controlled oscillators.
Proceedings of the 33rd European Solid-State Circuits Conference, 2004

2003
A Four-Wing Butterfly Attractor from a Fully Autonomous System.
Int. J. Bifurc. Chaos, 2003

Method of reducing contactor effect when testing high-precision ADCs.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Linear Model-Based Error Identification and Calibration for Data Converters.
Proceedings of the 2003 Design, 2003

2002
Chaotic communications with correlator receivers: theory and performance limits.
Proc. IEEE, 2002

Experimental Verification of the Butterfly Attractor in a Modified Lorenz System.
Int. J. Bifurc. Chaos, 2002

An equation for Generating Chaos and its monolithic Implementation.
Int. J. Bifurc. Chaos, 2002

Implementation of Model-Based Testing for Medium to High-Resolution Nyquist-Rate ADCs.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001
Process Deviations and Spot Defects: Two Aspects of Test and Test Development for Mixed-Signal Circuits.
J. Electron. Test., 2001

Recent results for chaotic modulation schemes.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
Digital communications using chaos.
Signal Process., 2000

Chua's circuit decomposition: a systematic design approach for chaotic oscillators.
J. Frankl. Inst., 2000

Systematic realization of a class of hysteresis chaotic oscillators.
Int. J. Circuit Theory Appl., 2000

Chaotic Modulation for Robust Digital Communications over Multipath Channels.
Int. J. Bifurc. Chaos, 2000

The Colpitts oscillator: Families of periodic solutions and their bifurcations.
Int. J. Bifurc. Chaos, 2000

Generic RC realizations of Chua's Circuit.
Int. J. Bifurc. Chaos, 2000

Model-based testing of high-resolution ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Frequency domain analysis of double sampling phase-locked loop.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Determination of main system parameters of FM-DCSK telecommunications system.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A system for chaos generation and its implementation in monolithic form.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Incorporation of Hard-Fault-Coverage in Model-Based Testing of Mixed-Signal ICs.
Proceedings of the 2000 Design, 2000

1999
A rigorous exposition of the LEMMA method for analog and mixed-signal testing.
IEEE Trans. Instrum. Meas., 1999

Chaotic Oscillator Configuration Using a Frequency Dependent Negative Resistor.
J. Circuits Syst. Comput., 1999

Enhanced versions of DCSK and FM-DCSK data transmission systems.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Simulation of the multipath performance of FM-DCSK digital communications using chaos.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Behavioral modeling of charge pump phase locked loops.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Classification of steady-state behavior of the Colpitts oscillator.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

Ultra-fast simulator developed in Matlab environment to evaluate multipath performance of FM-DCSK RF system.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

Design equations and baseband model for double-sampling phase-locked loop.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998
High frequency RC chaos generator.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

1993
Digital Signal Processor-Based Investigation of Chua's Circuit Family.
J. Circuits Syst. Comput., 1993

Bispectral Analysis of Chua's Circuit.
J. Circuits Syst. Comput., 1993

Synthesis of continuous three-segment voltage-controlled piecewise-linear resistors for Chua's circuit family using operational amplifiers, diodes and linear resistors.
Int. J. Circuit Theory Appl., 1993

Digital signal Processor-based Investigation of Chua's Circuit family.
Proceedings of the Chua's Circuit: A Paradigm for Chaos, 1993

Bispectral Analysis of Chua's Circuit.
Proceedings of the Chua's Circuit: A Paradigm for Chaos, 1993

1991
Hysteresis in electronic circuits: A circuit theorist's perspective.
Int. J. Circuit Theory Appl., 1991


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