Michael Payer

According to our database, Michael Payer authored at least 17 papers between 1980 and 2003.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2003

A Platform for Construction and Integration of Digital IP Blocks.

Michael Payer

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2003

2001

Industrial Experience with Formal Verification (Industrielle Erfahrungen mit Formaler Verifikation).

Michael Payer

Informationstechnik Tech. Inform., 2001

2000

Industrial Experience with Formal Verification.

Michael Payer

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Frankfurt, Germany, February 28, 2000

1995

Model Checking in Industrial Hardware Design.

Jörg Bormann, Jörg Lohse, Michael Payer, Gerd Venzl

Proceedings of the 32st Conference on Design Automation, 1995

1993

The Siemens high-level synthesis system CALLAS.

Jörg Biesenack, Michael Koster, Anton Langmaier, Stephane Ledeux, Sabine März, Michael Payer, Michael Pilsl, Steffen Rumler, Holger Soukup, Norbert Wehn, Peter Duzy

IEEE Trans. Very Large Scale Integr. Syst., 1993

1992

Allocation algorithms based on path analysis.

Reinaldo A. Bergamaschi, Raul Camposano, Michael Payer

Integr., 1992

Data Part Optimizations in the CALLAS Synthesis Environment.

Jörg Biesenack, Norbert Wehn, A. Stoll, Michael Payer

Proceedings of the Synthesis for Control Dominated Circuits, 1992

1991

Partitioning and ordering of CMOS circuits for switch level analysis.

Michael Payer

Integr., 1991

Scheduling under resource constraints and module assignment.

Reinaldo A. Bergamaschi, Raul Camposano, Michael Payer

Integr., 1991

Area and performance optimizations in path-based scheduling.

Reinaldo A. Bergamaschi, Raul Camposano, Michael Payer

Proceedings of the conference on European design automation, 1991

Data-Path Synthesis Using Path Analysis.

Reinaldo A. Bergamaschi, Raul Camposano, Michael Payer

Proceedings of the 28th Design Automation Conference, 1991

1989

Graphentheoretische Ansätze für CAD-Werkzeuge in der CMOS-Technik.

Michael Payer

PhD thesis, 1989

Finite State Machine Theory as a Tool for Construction of Systolic Arrays.

Michael Payer

Proceedings of the Computer Aided Systems Theory - EUROCAST'89, A Selection of Papers from the International Workshop EUROCAST'89, Las Palmas, Spain, February 26, 1989

1988

A system for estimation of numerical stability for matrix operations in systolic arrays.

Reinhard H. Rauscher, Peter Kückendahl, Michael Payer

Microprocess. Microprogramming, 1988

Hierarchische Zerlegung von Graphen mit zwei ausgezeichneten Knoten mit Anwendugen bei der Synthese und Analyse von MOS-Schaltungen.

Michael Payer

Proceedings of the GI, 1988

1987

Verification and validation of hierarchical CMOS gate array layouts.

Michael Payer

Microprocess. Microprogramming, 1987

1980

Systematischer Entwurf von Makroprozessoren.

Michael Payer

Proceedings of the GI - 10. Jahrestagung, Saarbrücken, 30. September, 1980