Michael Orshansky
Orcid: 0000-0002-6223-4748
According to our database1,
Michael Orshansky
authored at least 93 papers
between 1998 and 2024.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2015, "For contributions to VLSI design for manufacturability".
Timeline
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On csauthors.net:
Bibliography
2024
A Hierarchical Classification Method for High-accuracy Instruction Disassembly with Near-field EM Measurements.
ACM Trans. Embed. Comput. Syst., January, 2024
Proceedings of the 13th International Workshop on Hardware and Architectural Support for Security and Privacy, 2024
2023
IEEE Trans. Computers, February, 2023
CoRR, 2023
CoRR, 2023
Enhancing Cross-Category Learning in Recommendation Systems with Multi-Layer Embedding Training.
Proceedings of the Asian Conference on Machine Learning, 2023
2022
ACM J. Emerg. Technol. Comput. Syst., 2022
High-Level Simulation of Embedded Software Vulnerabilities to EM Side-Channel Attacks.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
Horizontal Side-Channel Vulnerabilities of Post-Quantum Key Exchange and Encapsulation Protocols.
ACM Trans. Embed. Comput. Syst., 2021
Galvanically Isolated, Power and Electromagnetic Side-Channel Attack Resilient Secure AES Core with Integrated Charge Pump based Power Management.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
Physical Design Strategies for Mitigating Fine-Grained Electromagnetic Side-Channel Attacks.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2020
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
Lattice PUF: A Strong Physical Unclonable Function Provably Secure against Machine Learning Attacks.
Proceedings of the 2020 IEEE International Symposium on Hardware Oriented Security and Trust, 2020
2019
Using Power-Anomalies to Counter Evasive Micro-Architectural Attacks in Embedded Systems.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019
2018
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017
2016
Variation-Tolerant Write Completion Circuit for Variable-Energy Write STT-RAM Architecture.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Exploiting randomness in sketching for efficient hardware implementation of machine learning applications.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
PolyGP: Improving GP-based analog optimization through accurate high-order monomials and semidefinite relaxation.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014
Enabling Efficient Analog Synthesis by Coupling Sparse Regression and Polynomial Optimization.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
Circuit-Level Timing-Error Acceptance for Design of Energy-Efficient DCT/IDCT-Based Systems.
IEEE Trans. Circuits Syst. Video Technol., 2013
BMC Syst. Biol., 2013
Proceedings of the International Symposium on Quality Electronic Design, 2013
Variable-energy write STT-RAM architecture with bit-wise write-completion monitoring.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013
Proceedings of the 18th IEEE European Test Symposium, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
Predictable Equation-Based Analog Optimization Based on Explicit Capture of Modeling Error Statistics.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Integr., 2012
IACR Cryptol. ePrint Arch., 2012
Embracing local variability to enable a robust high-gain positive-feedback amplifier: Design methodology and implementation.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Proceedings of the IEEE International Conference on IC Design & Technology, 2012
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
2011
Coupling timing objectives with optical proximity correction for improved timing yield.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
2010
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
An algorithm for exploiting modeling error statistics to enable robust analog optimization.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
SMATO: Simultaneous mask and target optimization for improving lithographic process window.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
A methodology for propagating design tolerances to shape tolerances for use in manufacturing.
Proceedings of the Design, Automation and Test in Europe, 2010
Ground rule slack aware tolerance-driven optical proximity correction for local metal interconnects.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2009
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
2008
Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
Series on integrated circuits and systems, Springer, ISBN: 978-0-387-30928-6, 2008
2007
A Statistical Algorithm for Power- and Timing-Limited Parametric Yield Optimization of Large Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
ACM Trans. Archit. Code Optim., 2007
Estimation of Leakage Power Consumption and Parametric Yield Based on Realistic Probabilistic Descriptions of Parameters.
J. Low Power Electron., 2007
CoRR, 2007
Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures, 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis.
Proceedings of the 44th Design Automation Conference, 2007
2006
Path-Based Statistical Timing Analysis Handling Arbitrary Delay Correlations: Theory and Implementation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Analysis of Leakage Power Reduction in Dual-Vth Technologies in the Presence of Large Threshold Voltage Variation.
J. Low Power Electron., 2006
Interval-based robust statistical techniques for non-negative convex functions, with application to timing analysis of computer chips.
Proceedings of the 2006 ACM Symposium on Applied Computing (SAC), 2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Proceedings of the 12th International Symposium on High-Performance Computer Architecture, 2006
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006
Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty.
Proceedings of the 43rd Design Automation Conference, 2006
Gain-based technology mapping for minimum runtime leakage under input vector uncertainty.
Proceedings of the 43rd Design Automation Conference, 2006
2005
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
An efficient algorithm for statistical minimization of total power under timing yield constraints.
Proceedings of the 42nd Design Automation Conference, 2005
2004
Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004
Proceedings of the 41th Design Automation Conference, 2004
2003
Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
2002
Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002
Proceedings of the 39th Design Automation Conference, 2002
2001
IEEE J. Solid State Circuits, 2001
2000
Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
1998
Proceedings of the 35th Conference on Design Automation, 1998