Michael Ogbonna Esonu
According to our database1,
Michael Ogbonna Esonu
authored at least 7 papers
between 1990 and 1995.
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Bibliography
1995
Area efficient computing structures for concurrent error detection in systolic arrays.
J. VLSI Signal Process., 1995
1994
Fault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison with CMOS & BiCMOS Circuits.
VLSI Design, 1994
1992
Design Methodology for Fault-Tolerant Systolic Array Architectures.
Proceedings of the 1992 International Conference on Parallel Processing, 1992
1991
Proceedings of the Fifth International Parallel Processing Symposium, Proceedings, Anaheim, California, USA, April 30, 1991
Area Efficient Computing Structures for Concurrent Error Detection in Systolic Architectures.
Proceedings of the International Conference on Parallel Processing, 1991
1990
Proceedings of the Second IEEE Symposium on Parallel and Distributed Processing, 1990