Michael Nicolaidis

Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Third workshop on dependable and secure nanocomputing.

[BibT_eX]

[DOI]

Jean Arlat

Cristian Constantinescu

Ravishankar K. Iyer

Johan Karlsson

Proceedings of the 2009 IEEE/IFIP International Conference on Dependable Systems and Networks, 2009

2008

Towards a holistic CAD platform for nanotechnologies.

[BibT_eX]

[DOI]

Eleftherios Kolonis

Microelectron. J., 2008

Low-Cost Highly-Robust Hardened Cells Using Blocking Feedback Transistors.

[BibT_eX]

[DOI]

Renaud Perez

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Special Session 2: Benchmarking and Standardization in Software-Based SER Characterization: Towards an IEEE Task Force?

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Second workshop on dependable and secure nanocomputing.

[BibT_eX]

[DOI]

Jean Arlat

Cristian Constantinescu

Ravishankar K. Iyer

Proceedings of the 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2008

2007

Defects Tolerant Logic Gates for Unreliable Future Nanotechnologies.

[BibT_eX]

[DOI]

Proceedings of the Computational and Ambient Intelligence, 2007

GRAAL: a new fault tolerant design paradigm for mitigating the flaws of deep nanometric technologies.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Test Conference, 2007

GRAAL: A Fault-Tolerant Architecture for Enabling Nanometric Technologies.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Workshop on Dependable and Secure Nanocomputing.

[BibT_eX]

[DOI]

Jean Arlat

Ravishankar K. Iyer

Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2007

2006

Session Abstract.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Multiple Defect Tolerant Devices for Unreliable Future Nanotechnologies.

[BibT_eX]

Cristiano Lazzari

Proceedings of the 7th Latin American Test Workshop, 2006

A Low-Cost Single-Event Latchup Mitigation Sscheme.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

From Nuclear Reaction to System Failures: Can We Address All Levels of Soft Errors Accurately?

[BibT_eX]

[DOI]

Nadine Buard

Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

A Transparent based Programmable Memory BIST.

[BibT_eX]

[DOI]

Proceedings of the 11th European Test Symposium, 2006

2005

Memory Defect Tolerance Architectures for Nanotechnologies.

[BibT_eX]

[DOI]

J. Electron. Test., 2005

Programmable memory BIST.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Design for Mitigation of Single Event Effects.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Radiation Induced Single-Word Multiple-Bit Upsets Correction in SRAM.

[BibT_eX]

[DOI]

Balkaran S. Gill

Christos A. Papachristou

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Simulation and Mitigation of Single Event Effects.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories.

[BibT_eX]

[DOI]

Balkaran S. Gill

Francis G. Wolff

Christos A. Papachristou

Steven L. Garverick

Proceedings of the 2005 Design, 2005

2004

Simulating Single Event Transients in VDSM ICs for Ground Level Radiation.

[BibT_eX]

[DOI]

J. Electron. Test., 2004

A Diversified Memory Built-In Self-Repair Approach for Nanotechnologies.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Evaluation of Memory Built-in Self Repair Techniques for High Defect Density Technologie.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2004), 2004

2003

Carry checking/parity prediction adders and ALUs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

Reliability Threats in VDSM - Shortcomings in Conventional Test and Fault-Tolerance Alternatives.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Memory Built-In Self-Repair for Nanotechnologies.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Dynamic Data-bit Memory Built-In Self- Repair.

[BibT_eX]

[DOI]

Slimane Boutobza

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

A Memory Built-In Self-Repair for High Defect Densities Based on Error Polarities.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Optimal Reconfiguration Functions for Column or Data-bit Built-In Self-Repair.

[BibT_eX]

[DOI]

Slimane Boutobza

Proceedings of the 2003 Design, 2003

2002

Guest Editorial.

[BibT_eX]

[DOI]

J. Electron. Test., 2002

Embedded Robustness IPs for Transient-Error-Free ICs.

[BibT_eX]

[DOI]

Eric Dupont

Peter Rohr

IEEE Des. Test Comput., 2002

Soft Error Protection for Embedded Memories.

[BibT_eX]

Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002

Robustness IPs for Reliability and Security of SoCs.

[BibT_eX]

[DOI]

Eric Dupont

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

New Methods for Evaluating the Impact of Single Event Transients in VDSM ICs.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

IP for Embedded Robustness.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

Embedded Robustness Ips.

[BibT_eX]

[DOI]

Eric Dupont

Peter Rohr

Proceedings of the 2002 Design, 2002

2001

Soft Errors and Tolerance for Soft Errors.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Designing and Implementing Efficient BISR Techniques for Embedded RAMs.

[BibT_eX]

Proceedings of the 2nd Latin American Test Workshop, 2001

Fail-Safe Synchronization Circuit for Duplicated Systems.

[BibT_eX]

[DOI]

Eleftherios Kolonis

Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

2000

Self-Checking Circuits versus Realistic Faults in Very Deep Submicron.

[BibT_eX]

[DOI]

Issam Alzaher-Noufal

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Evaluation of a Soft Error Tolerance Technique Based on Time and/or Space Redundancy.

[BibT_eX]

[DOI]

Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

ISIS: A Fail-Safe Interface Realized in Smart Power Technology.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000

Tutorial Statement.

[BibT_eX]

[DOI]

Chris W. H. Strolenberg

Kees Veelenturf

Proceedings of the 2000 Design, 2000

Cost Reduction and Evaluation of a Temporary Faults Detecting Technique.

[BibT_eX]

[DOI]

Proceedings of the 2000 Design, 2000

1999

Guest Editorial.

[BibT_eX]

[DOI]

Rob Roy

J. Electron. Test., 1999

Fault-Secure Parity Prediction Booth Multipliers.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 1999

A Digital BIST for Operational Amplifiers Embedded in Mixed-Signal Circuits.

[BibT_eX]

[DOI]

Iyad Rayane

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Built-In Current Sensor for IDDQ Testing in Deep Submicron CMOS.

[BibT_eX]

[DOI]

Th. Calin

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

A New Placement Algorithm Dedicated to Parallel Computers: Bases and Application.

[BibT_eX]

[DOI]

Fabien Clermidy

Thierry Collette

Proceedings of the 1999 Pacific Rim International Symposium on Dependable Computing (PRDC 1999), 1999

On-Line BIST for Testing Analog Circuits.

[BibT_eX]

[DOI]

Iyad Rayane

Proceedings of the IEEE International Conference On Computer Design, 1999

On Path Delay Fault Testing of Multiplexer - Based Shifters.

[BibT_eX]

[DOI]

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

A One-Bit-Signature BIST for Embedded Operational Amplifiers in Mixed-Signal Circuits Based on the Slew-Rate Detection.

[BibT_eX]

[DOI]

Iyad Rayane

Proceedings of the 1999 Design, 1999

A CAD Framework for Generating Self-Checking 1 Multipliers Based on Residue Codes.

[BibT_eX]

[DOI]

Issam Alzaher-Noufal

Proceedings of the 1999 Design, 1999

Scaling Deeper to Submicron: On-Line Testing to the Rescue.

[BibT_eX]

[DOI]

Proceedings of the 1999 Design, 1999

1998

Fail-Safe Interfaces for VLSI: Theoretical Foundations and Implementation.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1998

On-line testing for VLSI: state of the art and trends.

[BibT_eX]

[DOI]

Integr., 1998

On-Line Testing for VLSI - A Compendium of Approaches.

[BibT_eX]

[DOI]

J. Electron. Test., 1998

Efficient Totally Self-Checking Shifter Design.

[BibT_eX]

[DOI]

J. Electron. Test., 1998

Guest Editors' Introduction: Online VLSI Testing.

[BibT_eX]

Ramesh Karri

IEEE Des. Test Comput., 1998

Design for soft-error robustness to rescue deep submicron scaling.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Scaling Deeper to Submicron: On-Line Testing to the Rescue.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Current-based testing for analog and mixed-signal circuits.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Fault Detection for Linear Analog Circuits Using Current Injection.

[BibT_eX]

[DOI]

Th. Calin

Proceedings of the 1998 Design, 1998

Design of Fault-Secure Parity-Prediction Booth Multipliers.

[BibT_eX]

[DOI]

Proceedings of the 1998 Design, 1998

An Approach to the On-Line Testing of Operational Amplifiers.

[BibT_eX]

[DOI]

Marcelo Lubaszewski

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997

Fault-Secure Parity Prediction Arithmetic Operators.

[BibT_eX]

[DOI]

Salvador Manich

Joan Figueras

IEEE Des. Test Comput., 1997

On-Line Testing for VLSI.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Fault-secure shifter design: results and implementations.

[BibT_eX]

[DOI]

Proceedings of the European Design and Test Conference, 1997

1996

Theory of Transparent BIST for RAMs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1996

Enhancing realistic fault secureness in parity prediction array arithmetic operators by I<sub>DDQ</sub> monitoring.

[BibT_eX]

[DOI]

Salvador Manich

Joan Figueras

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Can Defect-Tolerant Chips Better Meet the Quality Challenge?

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Achieving Fault Secureness in Parity Prediction Arithmetic Operators: General Conditions and Implementations.

[BibT_eX]

[DOI]

Salvador Manich

Joan Figueras

Proceedings of the 1996 European Design and Test Conference, 1996

E-Groups: A New Technique for Fast Backward Propagation in System Level Test Generation.

[BibT_eX]

[DOI]

Rubin A. Parekhji

M. Boudjit

Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995

Testing complex couplings in multiport memories.

[BibT_eX]

[DOI]

Vladimir Castro Alves

IEEE Trans. Very Large Scale Integr. Syst., 1995

A strongly code disjoint built-in current sensor for strongly fault-secure static CMOS realizations.

[BibT_eX]

[DOI]

Jien-Chung Lo

James C. Daly

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Efficient UBIST implementation for microprocessor sequencing parts.

[BibT_eX]

[DOI]

J. Electron. Test., 1995

A tool for automatic generation of self-checking data paths.

[BibT_eX]

[DOI]

B. Hamdi

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

An Approach for Designing Total-Dose Tolerant MCMs Based on Current Monitoring.

[BibT_eX]

[DOI]

Fabian Vargas

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

Exact Aliasing Computation for RAM BIST.

[BibT_eX]

[DOI]

Vyacheslav N. Yarmolik

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

Upset-Tolerant CMOS SRAM Using Current Monitoring: Prototype and Test Experiments.

[BibT_eX]

[DOI]

Th. Calin

F. L. Vargas

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

Area versus detection latency trade-offs in self-checking memory design.

[BibT_eX]

[DOI]

Proceedings of the 1995 European Design and Test Conference, 1995

Analytic approach for error masking elimination in on-line multipliers.

[BibT_eX]

[DOI]

Alain Guyot

Proceedings of the 12th Symposium on Computer Arithmetic (ARITH-12 '95), 1995

1994

Fault secure property versus strongly code disjoint checkers.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Trade-offs in scan path and BIST implementations for RAMs.

[BibT_eX]

[DOI]

Vladimir Castro Alves

J. Electron. Test., 1994

Zero aliasing ROM BIST.

[BibT_eX]

[DOI]

Vyacheslav N. Yarmolik

J. Electron. Test., 1994

Efficient UBIST for RAMs.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Design for testability of on-line multipliers.

[BibT_eX]

[DOI]

Alain Guyot

Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Aliasing-free Signature Analysis for RAM BIST.

[BibT_eX]

[DOI]

Vyacheslav N. Yarmolik

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

SEU-Tolerant SRAM Design Based on Current Monitoring.

[BibT_eX]

[DOI]

F. L. Vargas

Proceedings of the Digest of Papers: FTCS/24, 1994

A Test Methodology Applied to Cellular Logic Programmable Gate Arrays.

[BibT_eX]

[DOI]

Proceedings of the Field-Programmable Logic, 1994

Efficient Implementations of Self-Checking Multiply and Divide Arrays.

[BibT_eX]

[DOI]

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993

Quiescent current estimation based on quality requirements.

[BibT_eX]

[DOI]

Fabian Luis Vargas

B. Hamdi

Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

Finitely self-checking circuits and their application on current sensors.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

Quiescent Current Monitoring to Improve the Reliability of Electronic Systems in Space Radiation Environments.

[BibT_eX]

[DOI]

F. L. Vargas

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Efficient Implementations of Self-Checking Adders and ALUs.

[BibT_eX]

[DOI]

Proceedings of the Digest of Papers: FTCS-23, 1993

1992

An SFS Berger check prediction ALU and its application to self-checking processor designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Improving the theory of truth table verification of iterative logic arrays.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

Transparent BIST for RAMs.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

A Tool for Automatic Generation of BISTed and Transparent BISTed Rams.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

Design of Static CMOS Self-Checking Circuits using Built-In Current Sensing.

[BibT_eX]

[DOI]

Jien-Chung Lo

James C. Daly

Proceedings of the Digest of Papers: FTCS-22, 1992

1991

Silicon compilation of hierarchical control sections with unified BIST testability.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 1991

Shorts in self-checking circuits.

[BibT_eX]

[DOI]

J. Electron. Test., 1991

New Implementations, Tools, and Experiments for Decreasing Self-Checking PLAs Area Overhead.

[BibT_eX]

[DOI]

M. Boudjit

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

Built-In Self-Test for Multi-Port RAMs.

[BibT_eX]

[DOI]

Vladimir Castro Alves

P. Lestrat

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

A self-checking PLA automatic generator tool based on unordered codes encoding.

[BibT_eX]

[DOI]

Kholdoun Torki

Antônio Otávio Fernandes

Proceedings of the conference on European design automation, 1991

1989

Self-exercising checkers for unified built-in self-test (UBIST).

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

Self-checking logic arrays.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 1989

A generalized theory of fail-safe systems.

[BibT_eX]

[DOI]

Serge Noraz

Proceedings of the Nineteenth International Symposium on Fault-Tolerant Computing, 1989

1988

Strongly Code Disjoint Checkers.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1988

UBIST version of the SYCO's control section compiler.

[BibT_eX]

[DOI]

Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

A unified built-in-test scheme: UBIST.

[BibT_eX]

[DOI]