Michael L. Bushnell

According to our database, Michael L. Bushnell authored at least 93 papers between 1984 and 2009.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2009

Variable Input Delay CMOS Logic for Low Power Design.

Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell

IEEE Trans. Very Large Scale Integr. Syst., 2009

2008

Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults.

Rajamani Sethuram, Michael L. Bushnell, Vishwani D. Agrawal

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

A Jitter Reduction Circuit Using Autocorrelation for Phase-Locked Loops and Serializer-Deserializer (SERDES) Circuits.

Hari Vijay Venkatanarayanan, Michael L. Bushnell

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2007

Graphical I_DDQ Signatures Reduce Defect Level and Yield Loss.

Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal

IEEE Trans. Very Large Scale Integr. Syst., 2007

Zero Cost Test Point Insertion Technique for Structured ASICs.

Rajamani Sethuram, Seongmoon Wang, Srimat T. Chakradhar, Michael L. Bushnell

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

A Neural Net Branch Predictor to Reduce Power.

Rajamani Sethuram, Omar I. Khan, Hari Vijay Venkatanarayanan, Michael L. Bushnell

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Architecture for Variable-Length Combined FFT, DCT, and MWT Transform Hardware for a Multi-ModeWireless System.

Rohit Pandey, Michael L. Bushnell

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Fault Models and Device Yield of a Large Population of Room Temperature Operation Single-Electron Transistors.

Daniel Mazor, Michael L. Bushnell, David J. Mulligan, Richard J. Blaikie

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Test Pattern Generation Using Modulation by Haar Wavelets and Correlation for Sequential BIST.

Suresh Kumar Devanathan, Michael L. Bushnell

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Analog Circuit Testing Using Auto Regressive Moving Average Models.

Jeffrey Ayres, Michael L. Bushnell

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

SPARTAN: a spectral and information theoretic approach to partial-scan.

Omar I. Khan, Michael L. Bushnell, Suresh Kumar Devanathan, Vishwani D. Agrawal

Proceedings of the 2007 IEEE International Test Conference, 2007

Power Grid Analysis of Dynamic Power Cutoff Technology.

Baozhen Yu, Michael L. Bushnell

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

Transistor Sizing of Logic Gates to Maximize Input Delay Variability.

Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell

J. Low Power Electron., 2006

An Area Efficient Mixed-Signal Test Architecture for Systems-on-a-Chip.

Hari Vijay Venkatanarayanan, Michael L. Bushnell

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Aliasing Analysis of Spectral Statistical Response Compaction Techniques.

Omar I. Khan, Michael L. Bushnell

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Sequential Spectral ATPG Using the Wavelet Transform and Compaction.

Suresh Kumar Devanathan, Michael L. Bushnell

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Analog Macromodeling for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults.

Shweta Chary, Michael L. Bushnell

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Automatic Path-Delay Fault Test Generation for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults.

Shweta Chary, Michael L. Bushnell

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

A novel dynamic power cutoff technique (DPCT) for active leakage reduction in deep submicron CMOS circuits.

Baozhen Yu, Michael L. Bushnell

Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Zero Cost Test Point Insertion Technique to Reduce Test Set Size and Test Generation Time for Structured ASICs.

Rajamani Sethuram, Seongmoon Wang, Srimat T. Chakradhar, Michael L. Bushnell

Proceedings of the 15th Asian Test Symposium, 2006

2005

Using Contrapositive Law in an Implication Graph to Identify Logic Redundancies.

Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Design of Variable Input Delay Gates for Low Dynamic Power Circuits.

Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell

Proceedings of the Integrated Circuit and System Design, 2005

2004

A New Classification of Path-Delay Fault Testability in Terms of Stuck-at Faults.

Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell

J. Comput. Sci. Technol., 2004

CMOS Circuit Design for Minimum Dynamic Power and Highest Speed.

Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

A Tuturial on the Emerging Nanotechnology Devices.

Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

On Random Pattern Generation with the Selfish Gene Algorithm for Testing Digital Sequential Circuits.

Junwu Zhang, Michael L. Bushnell, Vishwani D. Agrawal

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Spectral Analysis for Statistical Response Compaction During Built-In Self-Testing.

Omar I. Khan, Michael L. Bushnell

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003

New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss.

Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program.

Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

A Fault-Independent Transitive Closure Algorithm for Redundancy Identification.

Vishal J. Mehta, Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

2002

Electronic Testing for SOC Designers (Tutorial Abstract).

Vishwani D. Agrawal, Michael L. Bushnell

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Analog Macromodeling of Capacitive Coupling Faults in Digital Circuit Interconnects.

Aditya D. Sathe, Michael L. Bushnell, Vishwani D. Agrawal

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

A New Transitive Closure Algorithm with Application to Redundancy Identification.

Vivek Gaur, Vishwani D. Agrawal, Michael L. Bushnell

Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

2001

A Code Transition Delay Model for ADC Test.

Sanjay Mohan, Michael L. Bushnell

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

2000

Improving path delay testability of sequential circuits.

Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell

IEEE Trans. Very Large Scale Integr. Syst., 2000

Path delay fault simulation of sequential circuits.

Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell

IEEE Trans. Very Large Scale Integr. Syst., 2000

False-Path Removal Using Delay Fault Simulation.

Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell, Carlos G. Parodi

J. Electron. Test., 2000

1999

Test Generation for Mixed-Signal Devices Using Signal Flow Graphs.

Rajesh Ramadoss, Michael L. Bushnell

J. Electron. Test., 1999

Effect of Noise on Analog Circuit Testing.

Madhu K. Iyer, Michael L. Bushnell

J. Electron. Test., 1999

A Complete Characterization of Path Delay Faults through Stuck-at Faults.

Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method.

Vishwani D. Agrawal, Michael L. Bushnell, Ganapathy Parthasarathy, Rajesh Ramadoss

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Increasing Test Coverage in a VLSI Design Course.

Michael L. Bushnell

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998

A parallel-vector concurrent-fault simulator and generation of single-input-change tests for path-delay faults.

Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

The path-status graph with application to delay fault simulation.

Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits.

Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas

J. Electron. Test., 1998

Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion.

Ganapathy Parthasarathy, Michael L. Bushnell

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

On Delay-Untestable Paths and Stuck-Fault Redundancy.

Subhashis Majumder, Vishwani D. Agrawal, Michael L. Bushnell

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

Path Delay Testing: Variable-Clock Versus Rated-Clock.

Subhashis Majumder, Michael L. Bushnell, Vishwani D. Agrawal

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

A non-enumerative path delay fault simulator for sequential circuits.

Carlos G. Parodi, Vishwani D. Agrawal, Michael L. Bushnell, Shianling Wu

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

False-Path Removal Using Delay Fault Simulation.

Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997

Improving a nonenumerative method to estimate path delay fault coverage.

Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell, Janak H. Patel

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

On variable clock methods for path delay testing of sequential circuits.

Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests.

Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal

J. Electron. Test., 1997

A Functional Decomposition Method for Redundancy Identification and Test Generation.

Michael L. Bushnell, John Giraldi

J. Electron. Test., 1997

Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation.

Mandyam-Komar Srinivas, Michael L. Bushnell, Vishwani D. Agrawal

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1996

Sequential circuit test generation using dynamic justification equivalence.

Xinghao Chen, Michael L. Bushnell

J. Electron. Test., 1996

Statistical path delay fault coverage estimation for synchronous sequential circuits.

Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Parallel concurrent path-delay fault simulation using single-input change patterns.

Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

An Exact Non-Enumerative Fault Simulator for Path-Delay Faults.

Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Redundancy Identification Using Transitive Closure.

Vishwani D. Agrawal, Michael L. Bushnell, Qing Lin

Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995

Fault coverage estimation by test vector sampling.

Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming .

Imtiaz P. Shaik, Michael L. Bushnell

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

An asynchronous algorithm for sequential circuit test generation on a network of workstations.

James Sienicki, Michael L. Bushnell, Prathima Agrawal, Vishwani D. Agrawal

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

A graph approach to DFT hardware placement for robust delay fault BIST.

Imtiaz P. Shaik, Michael L. Bushnell

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Statistical methods for delay fault coverage analysis.

Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Generation of search state equivalence for automatic test pattern generation.

Xinghao Chen, Michael L. Bushnell

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests.

Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

An adaptive distributed algorithm for sequential circuit test generation.

James Sienicki, Michael L. Bushnell, Prathima Agrawal, Vishwani D. Agrawal

Proceedings of the Proceedings EURO-DAC'95, 1995

Functional test generation for path delay faults.

Mandyam-Komar Srinivas, Vishwani D. Agrawal, Michael L. Bushnell

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1994

Energy minimization and design for testability.

Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell

J. Electron. Test., 1994

FACTS: fault coverage estimation by test vector sampling.

Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell

Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Neural models for transistor and mixed-level test generation.

Carolina L. C. Cooper, Michael L. Bushnell

Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Graphical Methodology Language for CAD Frameworks.

James Sienicki, Michael L. Bushnell, Sandip Parikh

Proceedings of the Seventh International Conference on VLSI Design, 1994

Dynamic State and Objective Learning for Sequential Circuit Automatic Test Generation Using Decomposition Equivalence.

Xinghao Chen, Michael L. Bushnell

Proceedings of the Digest of Papers: FTCS/24, 1994

Distributed Computing, Automatic Design, and Error Recovery in the ULYSSES II Framework.

Sandip Parikh, Michael L. Bushnell, James Sienicki, Ganesh Ramakrishnan

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

An Efficient Path Delay Fault Coverage Estimator.

Keerthi Heragu, Michael L. Bushnell, Vishwani D. Agrawal

Proceedings of the 31st Conference on Design Automation, 1994

1993

Design for Testability for Path Delay faults in Sequential Circuits.

Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992

A solvable class of quadratic 0-1 programming.

Srimat T. Chakradhar, Michael L. Bushnell

Discret. Appl. Math., 1992

Delay Fault Models and Test Generation for Random Logic Sequential Circuits.

Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell

Proceedings of the 29th Design Automation Conference, 1992

1991

Search State Equivalence for Redundancy Identification and Test Generation.

John Giraldi, Michael L. Bushnell

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1990

Toward massively parallel automatic test generation.

Srimat T. Chakradhar, Michael L. Bushnell, Vishwani D. Agrawal

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Neural Net and Boolean Satisfiability Models of Logic Circuits.

Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell, Thomas K. Truong

IEEE Des. Test Comput., 1990

Polynomial time solvable fault detection problems.

Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell

Proceedings of the 20th International Symposium on Fault-Tolerant Computing, 1990

EST: The New Frontier in Automatic Test-Pattern Generation.

John Giraldi, Michael L. Bushnell

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

Automatic Test Generation Using Quadratic 0-1 Programming.

Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

MHERTZ: A New Optimization Algorithm for Floorplanning and Global Routing.

Daniel R. Brasen, Michael L. Bushnell

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989

Automated design tool execution in the Ulysses design environment.

Michael L. Bushnell, Stephen W. Director

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

1988

Automatic test generation using neural networks.

Srimat T. Chakradhar, Michael L. Bushnell, Vishwani D. Agrawal

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

A Module Area Estimator for VLSI Layout.

Xinghao Chen, Michael L. Bushnell

Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987

ULYSSES - a knowledge-based VLSI design environment.

Michael L. Bushnell, Stephen W. Director

Artif. Intell. Eng., 1987

1986

Guest editorial.

Michael L. Bushnell, Pierre Haren

Artif. Intell. Eng., 1986

VLSI CAD tool integration using the Ulysses environment.

Michael L. Bushnell, Stephen W. Director

Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

1984

DIF: A framework for VLSI multi-level representation.

David P. LaPotin, Sani R. Nassif, Jayanth V. Rajan, Michael L. Bushnell, John A. Nestor

Integr., 1984