Michael Janiaut

According to our database1, Michael Janiaut authored at least 5 papers between 2004 and 2009.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

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Bibliography

2009
An Embedded and Programmable System Based FPGA for Real Time MPEG Stream Buffer Analysis.
IEEE Trans. Circuits Syst. Video Technol., 2009

2005
Configurable hardware implementation of a conceptual decoder for a real-time MPEG-2 analysis.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004
SystemC Model of a MPEG-2 DVB-T Bit-Rate Measurement Architecture for FPGA Implementation.
Proceedings of the 15th IEEE International Workshop on Rapid System Prototyping (RSP 2004), 2004

FPGA Implementation of a Novel All Digital PLL Architecture for PCR Related Measurements in DVB-T.
Proceedings of the Field Programmable Logic and Application, 2004

FPGA Implementation of a Novel Architecture for PCR Related Measurements In DVB-T.
Proceedings of the International Conference on Embedded Systems and Applications, 2004


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