Michael Guilherme Jordan

Orcid: 0000-0002-5776-2626

Affiliations:
  • Federal University of Rio Grande do Sul, Porto Alegre, Brazil


According to our database1, Michael Guilherme Jordan authored at least 35 papers between 2017 and 2024.

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Bibliography

2024
TARA: Enhancing Real-Time Network Traffic Classification with Hardware Virtual Layers.
Proceedings of the 37th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design, 2024

ADARE: Adaptive Resource Provisioning in Multi-FPGA Edge Environments.
Proceedings of the 37th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design, 2024

2023
Multiprovision: a Design Space Exploration tool for multi-tenant resource provisioning in CPU-GPU environments.
Des. Autom. Embed. Syst., December, 2023

MVSym: Efficient symbiotic exploitation of HLS-kernel multi-versioning for collaborative CPU-FPGA cloud systems.
Integr., November, 2023

Energy-aware fully-adaptive resource provisioning in collaborative CPU-FPGA cloud environments.
J. Parallel Distributed Comput., June, 2023

Dynamic Offloading for Improved Performance and Energy Efficiency in Heterogeneous IoT-Edge-Cloud Continuum.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

Design Space Exploration for CNN Offloading to FPGAs at the Edge.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

Resource Provisioning for CPU-FPGA Environments with Adaptive HLS-Versioning and DVFS.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

Pruning and Early-Exit Co-Optimization for CNN Acceleration on FPGAs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Adaptive Inference on Reconfigurable SmartNICs for Traffic Classification.
Proceedings of the Advanced Information Networking and Applications, 2023

2022
ERIN: Energy-Aware Resource-Provisioning Framework for CPU-FPGA Multitenant Environment.
IEEE Des. Test, 2022

An energy efficient multi-target binary translator for instruction and data level parallelism exploitation.
Des. Autom. Embed. Syst., 2022

On the benefits of Collaborative Thread Throttling and HLS-Versioning in CPU-FPGA Environments.
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022

ConfAx: Exploiting Approximate Computing for Configurable FPGA CNN Acceleration at the Edge.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

AdaFlow: A Framework for Adaptive Dataflow CNN Acceleration on FPGAs.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Synergistically Exploiting CNN Pruning and HLS Versioning for Adaptive Inference on Multi-FPGAs at the Edge.
ACM Trans. Embed. Comput. Syst., 2021

Resource-Aware Collaborative Allocation for CPU-FPGA Cloud Environments.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Dynamic concurrency throttling on NUMA systems and data migration impacts.
Des. Autom. Embed. Syst., 2021

TRIPP: Transparent Resource Provisioning for Multi-Tenant CPU-GPU based Cloud Environments.
Proceedings of the XI Brazilian Symposium on Computing Systems Engineering, 2021

ETCF - Energy-Aware CPU Thread Throttling and Workload Balancing Framework for CPU-FPGA Collaborative Environments.
Proceedings of the XI Brazilian Symposium on Computing Systems Engineering, 2021

FAIR: Fully-Adaptive Framework for Improving Resource Provisioning in Collaborative CPU-FPGA Cloud Environments.
Proceedings of the 33rd IEEE International Symposium on Computer Architecture and High Performance Computing, 2021

Exploiting HLS-Generated Multi-Version Kernels to Improve CPU-FPGA Cloud Systems.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
Data clustering for efficient approximate computing.
Des. Autom. Embed. Syst., 2020

A Management Technique for Concurrent Access to a Reconfigurable Accelerator.
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020

Firefly: An Open-source Rocket-based Intermittent Framework.
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020

Unlocking the Full Potential of Heterogeneous Accelerators by Using a Hybrid Multi-Target Binary Translator.
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020

MCEA: A Resource-Aware Multicore CGRA Architecture for the Edge.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

2019
On the influence of Data Migration in Dynamic Thread Management of Parallel Applications.
Proceedings of the IX Brazilian Symposium on Computing Systems Engineering, 2019

A Runtime Power-Aware Phase Predictor for CGRAs.
Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019

Power-Aware Phase Oriented Reconfigurable Architecture.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Boosting SIMD Benefits through a Run-time and Energy Efficient DLP Detection.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Runtime Vectorization of Conditional Code and Dynamic Range Loops to ARM NEON Engine.
Proceedings of the VIII Brazilian Symposium on Computing Systems Engineering, 2018

Improving Software Productivity and Performance Through a Transparent SIMD Execution.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

Exploiting Partial Reconfiguration on a Dynamic Coarse Grained Reconfigurable Architecture.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017
A framework to automatically generate heterogeneous organization reconfigurable multiprocessing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017


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