Michael F. Dossis

Proceedings of the 8th South-East Europe Design Automation, 2023

Assessing Swapping Policies as a Detailed Placement Approach.

[BibT_eX]

[DOI]

Ioannis Arvanitakis

Athanasios Kakarountas

Proceedings of the 8th South-East Europe Design Automation, 2023

2022

Exploiting Net Connectivity in Legalization and Detailed Placement Scenarios.

[BibT_eX]

[DOI]

Inf., 2022

Behavioural synthesis of SGD using the CCC framework: a simple XOR-solving MLP.

[BibT_eX]

[DOI]

Appl. Intell., 2022

High Throughput of Image Processing with Keccak Algorithm using Microprocessor on FPGA.

[BibT_eX]

[DOI]

Argyrios Sideris

Theodora Sanida

Antonios Chatzisavvas

Minas Dasygenis

Proceedings of the 7th South-East Europe Design Automation, 2022

Radiography Images with Transfer Learning on Embedded System.

[BibT_eX]

[DOI]

Theodora Sanida

Argyrios Sideris

Antonios Chatzisavvas

Minas Dasygenis

Proceedings of the 7th South-East Europe Design Automation, 2022

Greek Parliament Members on Instagram: A study on building a political image.

[BibT_eX]

[DOI]

Ifigeneia Mylona

Proceedings of the 7th South-East Europe Design Automation, 2022

Scavenging PyPi for VLSI Packages.

[BibT_eX]

[DOI]

Proceedings of the 7th South-East Europe Design Automation, 2022

Deep Neural Network Applications for Bioinformatics.

[BibT_eX]

[DOI]

Konstantina Vaitsi

Proceedings of the 7th South-East Europe Design Automation, 2022

Social Media and Consumer Behaviour: Exploratory Factor Analysis.

[BibT_eX]

[DOI]

Ifigeneia Mylona

Proceedings of the 7th South-East Europe Design Automation, 2022

A gene visualising database.

[BibT_eX]

[DOI]

Kyriakos Kydoniefs

Proceedings of the 7th South-East Europe Design Automation, 2022

Brain MRI based diagnosis of autoimmune diseases using deep learning.

[BibT_eX]

[DOI]

Georgios Chatzisavvas

Proceedings of the 7th South-East Europe Design Automation, 2022

Near Data Processing Performance Improvement Prediction via Metric-Based Workload Classification.

[BibT_eX]

[DOI]

Dimitrios Papalekas

Athanasios Tziouvaras

George Floros

Proceedings of the 11th International Conference on Modern Circuits and Systems Technologies, 2022

2021

STEAM in VET - An ArcGIS StoryMap Approach.

[BibT_eX]

[DOI]

Proceedings of the 6th South-East Europe Design Automation, 2021

Redesign, Extensibility & Evaluation of a Placement Utilities Toolset.

[BibT_eX]

[DOI]

George Floros

Proceedings of the 6th South-East Europe Design Automation, 2021

Converging Formal Verification in a High-Level Synthesis Environment.

[BibT_eX]

[DOI]

Proceedings of the 6th South-East Europe Design Automation, 2021

Variations on a Connectivity-based Legalizer for Standard Cell Design.

[BibT_eX]

[DOI]

Proceedings of the 6th South-East Europe Design Automation, 2021

Juxtaposing Vivado Design Flows in Batch Mode.

[BibT_eX]

[DOI]

Proceedings of the PCI 2021: 25th Pan-Hellenic Conference on Informatics, Volos, Greece, November 26, 2021

Branchless Code Generation for Modern Processor Architectures.

[BibT_eX]

[DOI]

Alexandros Angelou

Proceedings of the PCI 2021: 25th Pan-Hellenic Conference on Informatics, Volos, Greece, November 26, 2021

2020

Preliminary results of a proposed CNN framework for use in motorway applicable detection systems.

[BibT_eX]

[DOI]

George Sisias

Sotirios Kontogiannis

Myrto Konstantinidou

Proceedings of the 5th South-East Europe Design Automation, 2020

A Novel Genetic Algorithm for I/O Pad Planning Retaining Former Cell Positions.

[BibT_eX]

[DOI]

Taxiarchis G. Kouskouras

Vasileios Dimitriadis

Proceedings of the 5th South-East Europe Design Automation, 2020

Global and Pointer Variables in High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 5th South-East Europe Design Automation, 2020

The CCC framework: Training and inference of a simple MLP for the XOR problem.

[BibT_eX]

[DOI]

Proceedings of the 5th South-East Europe Design Automation, 2020

Rapid, Formal Verification with Automated and Executable, Cycle-accurate simulators, and Generated Testbenches.

[BibT_eX]

[DOI]

Proceedings of the PCI 2020: 24th Pan-Hellenic Conference on Informatics, 2020

Adaptive Operation-Based ALU and FPU Clocking.

[BibT_eX]

[DOI]

Athanassios Tziouvaras

Proceedings of the 9th International Conference on Modern Circuits and Systems Technologies, 2020

2019

Instruction-Based Timing Analysis in Pipelined Processors.

[BibT_eX]

[DOI]

Athanassios Tziouvaras

Proceedings of the 4th South-East Europe Design Automation, 2019

A Convolutional Neural Network for Sentiment Analysis of TripAdvisor reviews.

[BibT_eX]

[DOI]

Ifigeneia Mylona

Proceedings of the 4th South-East Europe Design Automation, 2019

High Level Synthesis of CART.

[BibT_eX]

[DOI]

Proceedings of the 4th South-East Europe Design Automation, 2019

2018

Resolving Loop Pipelining Issues in the CCC High-level Synthesis E-CAD Framework.

[BibT_eX]

[DOI]

Proceedings of the 41st International Conference on Telecommunications and Signal Processing, 2018

Operation Dependencies in Loop Pipelining for High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2018 South-Eastern European Design Automation, 2018

Performance evaluation on IoT devices secure data delivery processes.

[BibT_eX]

[DOI]

Ioannis Georgiadis

Sotirios Kontogiannis

Proceedings of the 22nd Pan-Hellenic Conference on Informatics, 2018

Proposed open source framework for interactive IoT smart museums.

[BibT_eX]

[DOI]

Sotirios Kontogiannis

Proceedings of the 22nd Pan-Hellenic Conference on Informatics, 2018

2017

Optimal Model Parameters of Inverse Kinematics Solution of a 3R Robotic Manipulator Using ANN Models.

[BibT_eX]

[DOI]

Nikolaos E. Karkalos

Angelos P. Markopoulos

Int. J. Manuf. Mater. Mech. Eng., 2017

Loop pipelining in high-level synthesis with CCC.

[BibT_eX]

[DOI]

Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017

2016

Gamifying e-learning as a Means of Overcoming Its Deficiencies.

[BibT_eX]

[DOI]

Angelos P. Markopoulos

Anastasios Fragkou

Petros D. Kasidiaris

Proceedings of the SouthEast European Design Automation, 2016

Source-Level Compiler Optimizations for High-Level Synthesis.

[BibT_eX]

[DOI]

Georgios Chatzianastasiou

Apostolos Tsakyridis

Proceedings of the SouthEast European Design Automation, 2016

2015

Performance and power simulation of a functional-unit-network processor with simplescalar and wattch.

[BibT_eX]

[DOI]

Kleovoulos Kalaitzidis

Proceedings of the 19th Panhellenic Conference on Informatics, 2015

Hardware synthesis of high-level C constructs.

[BibT_eX]

[DOI]

Proceedings of the 19th Panhellenic Conference on Informatics, 2015

2014

A Floating-Point Paradigm for High-level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 18th Panhellenic Conference on Informatics, 2014

2013

Formal Methods in High-Level and System Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Semantic Hyper/Multimedia Adaptation - Schemes and Applications, 2013

Modeling and simulation in a formal design framework.

[BibT_eX]

[DOI]

Proceedings of the Balkan Conference in Informatics, 2013

2012

Formal ESL Synthesis for Control-Intensive Applications.

[BibT_eX]

[DOI]

Adv. Softw. Eng., 2012

2011

Use of Behavioral Synthesis to Implement a Cellular Neural Network for Image Processing Applications.

[BibT_eX]

[DOI]

Proceedings of the 15th Panhellenic Conference on Informatics, 2011

2010

Intermediate Predicate Format for Design Automation Tools.

[BibT_eX]

[DOI]

J. Next Gener. Inf. Technol., 2010

Provably-Correct, Behavioural High-Level Synthesis of Program Accelerators via the Web.

[BibT_eX]

[DOI]

J. Next Gener. Inf. Technol., 2010

Automated Extraction of Hardware Accelerators Via an Intelligent Knowledge-based System.

[BibT_eX]

[DOI]

Int. J. Intell. Inf. Process., 2010

Using an XML schema to validate a formal hardware compiler.

[BibT_eX]

[DOI]

Proceedings of the 5th International Workshop on Semantic Media Adaptation and Personalization, 2010

Automatic Generation of Massively Parallel Hardware from Control-Intensive Sequential Programs.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Synthesis of provably-correct hardware with options.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009

A Web Service to Generate Program Coprocessors.

[BibT_eX]

[DOI]

T. Themelis

L. Markopoulos

Proceedings of the 4th International Workshop on Semantic Media Adaptation and Personalization, 2009

1999

Provably Correct Hardware Compilation using Timing Diagrams.

[BibT_eX]

Michael Schenke

Proceedings of the Formal Methods for Protocol Engineering and Distributed Systems, 1999

1994

Synthesis of Customized Hardware from ADA.

[BibT_eX]

[DOI]