Michael Clinton

According to our database, Michael Clinton authored at least 11 papers between 2007 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2018

A 5GHz 7nm L1 cache memory compiler for high-speed computing and mobile applications.

Michael Clinton, Rajinder Singh, Marty Tsai, Shayan Zhang, Bryan Sheffield, Jonathan Chang

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017

12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications.

Michael Clinton, Hank Cheng, Hung-Jen Liao, Robin Lee, Ching-Wei Wu, Johnny Yang, Hau-Tai Hsieh, Frank Wu, Jung-Ping Yang, Atul Katoch, Arun Achyuthan, Donald Mikan, Bryan Sheffield, Jonathan Chang

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2014

An FRAM-Based Nonvolatile Logic MCU SoC Exhibiting 100% Digital State Retention at <i>VDD</i> = 0 V Achieving Zero Leakage With < 400-ns Wakeup Time for ULP Applications.

Sudhanshu Khanna, Steven Bartling, Michael Clinton, Scott R. Summerfelt, John A. Rodriguez, Hugh P. McAdams

IEEE J. Solid State Circuits, 2014

2013

Session 18 overview: Advanced embedded SRAM.

Michael Clinton, Atsushi Kawasumi

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

An 8MHz 75µA/MHz zero-leakage non-volatile logic-based Cortex-M0 MCU SoC exhibiting 100% digital state retention at VDD=0V with <400ns wakeup and sleep transitions.

Steven Bartling, Sudhanshu Khanna, Michael Clinton, Scott R. Summerfelt, John A. Rodriguez, Hugh P. McAdams

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012

A Low-Voltage 1 Mb FRAM in 0.13 µm CMOS Featuring Time-to-Digital Sensing for Expanded Operating Margin.

Masood Qazi, Michael Clinton, Steven Bartling, Anantha P. Chandrakasan

IEEE J. Solid State Circuits, 2012

Session 13 overview: High-performance embedded SRAM: Memory subcommittee.

Leland Chang, Michael Clinton

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011

A low-voltage 1Mb FeRAM in 0.13μm CMOS featuring time-to-digital sensing for expanded operating margin in scaled CMOS.

Masood Qazi, Michael Clinton, Steven Bartling, Anantha P. Chandrakasan

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Design and technology interaction beyond 32nm.

Michael Clinton, Clive Bittlestone, G. Girishankar, Viet Le, Vinod Menezes

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2008

A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques.

Gordon Gammie, Alice Wang, Minh Chau, Sumanth Gururajarao, Robert Pitts, Fabien Jumel, Stacey Engel, Philippe Royannez, Rolf Lagerquist, Hugh Mair, Jeff Vaccani, Greg Baldwin, Keerthi Heragu, Rituparna Mandal, Michael Clinton, Don Arden, Uming Ko

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007

Solutions for logic and processor core design at the 45nm technology node & and below.

Philippe Royannez, Hugh Mair, Michael Clinton, Uming Ko

Proceedings of the 14th IEEE International Conference on Electronics, 2007