Michael C. Huang

CoRR, 2024

HyperTEE: A Decoupled TEE Architecture with Secure Enclave Management.

[BibT_eX]

[DOI]

Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024

DS-GL: Advancing Graph Learning via Harnessing Nature's Power within Scalable Dynamical Systems.

[BibT_eX]

[DOI]

Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

Extending Power of Nature from Binary to Real-Valued Graph Learning in Real World.

[BibT_eX]

[DOI]

Proceedings of the Twelfth International Conference on Learning Representations, 2024

2023

Efficient LDPC Decoding using Physical Computation.

[BibT_eX]

[DOI]

CoRR, 2023

Augmented Electronic Ising Machine as an Effective SAT Solver.

[BibT_eX]

[DOI]

CoRR, 2023

Combining Cubic Dynamical Solvers with Make/Break Heuristics to Solve SAT.

[BibT_eX]

[DOI]

Matthew Burns

Proceedings of the 26th International Conference on Theory and Applications of Satisfiability Testing, 2023

Supporting Energy-based Learning with an Ising Machine substrate: a Case Study on RBM.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

Ising-CF: A Pathbreaking Collaborative Filtering Method Through Efficient Ising Machine Learning.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Ising-Traffic: Using Ising Machine Learning to Predict Traffic Congestion under Uncertainty.

[BibT_eX]

[DOI]

Proceedings of the Thirty-Seventh AAAI Conference on Artificial Intelligence, 2023

2022

Irrelevant Data Traffic in Modern Low Power GPU Architectures.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Networking, Architecture and Storage, 2022

LoopIn: A Loop-Based Simulation Sampling Mechanism.

[BibT_eX]

[DOI]

Proceedings of the International IEEE Symposium on Performance Analysis of Systems and Software, 2022

A CMOS Compatible Bistable Resistively-coupled Ising Machine-BRIM.

[BibT_eX]

[DOI]

Richard Afoakwa

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Increasing ising machine capacity with multi-chip architectures.

[BibT_eX]

[DOI]

Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

QuBRIM: A CMOS Compatible Resistively-Coupled Ising Machine with Quantized Nodal Interactions.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

HyBP: Hybrid Isolation-Randomization Secure Branch Predictor.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

2021

Exploiting Security Dependence for Conditional Speculation Against Spectre Attacks.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2021

BRIM: Bistable Resistively-Coupled Ising Machine.

[BibT_eX]

[DOI]

Richard Afoakwa

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

A Lightweight Isolation Mechanism for Secure Branch Predictors.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

CMOS Ising Machines with Coupled Bistable Nodes.

[BibT_eX]

[DOI]

Richard Afoakwa

CoRR, 2020

2019

Concurrent Multipoint-to-Multipoint Communication on Interposer Channels.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

R3-DLA (Reduce, Reuse, Recycle): A More Efficient Approach to Decoupled Look-Ahead Architectures.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

To Stack or Not To Stack.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019

2018

Venice: An Effective Resource Sharing Architecture for Data Center Servers.

[BibT_eX]

[DOI]

ACM Trans. Comput. Syst., 2018

A Case for a More Effective, Power-Efficient Turbo Boosting.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2018

Bootstrapping: Using SMT Hardware to Improve Single-Thread Performance.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2018

Hadoop Configuration Tuning With Ensemble Modeling and Metaheuristic Optimization.

[BibT_eX]

[DOI]

Xingcheng Hua

IEEE Access, 2018

High Swing Pulse-Amplitude Modulation of Transmission Line Links for On-Chip Communication.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Division of Labor: A More Effective Approach to Prefetching.

[BibT_eX]

[DOI]

Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

2017

Redundant Memory Array Architecture for Efficient Selective Protection.

[BibT_eX]

[DOI]

Ruohuang Zheng

Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

T2: A Highly Accurate and Energy Efficient Stride Prefetcher.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

DRUT: An Efficient Turbo Boost Solution via Load Balancing in Decoupled Look-Ahead Architecture.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

2016

Building Expressive and Area-Efficient Directories with Hybrid Representation and Adaptive Multi-Granular Tracking.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

Thread-Aware Adaptive Prefetcher on Multicore Systems: Improving the Performance for Multithreaded Workloads.

[BibT_eX]

[DOI]

Jiyang Yu

ACM Trans. Archit. Code Optim., 2016

Heterogeneous 3-D circuits: Integrating free-space optics with CMOS.

[BibT_eX]

[DOI]

Microelectron. J., 2016

Threads and Data Mapping: Affinity Analysis for Traffic Reduction.

[BibT_eX]

[DOI]

Qi Hu

IEEE Comput. Archit. Lett., 2016

Hardware support for protective and collaborative cache sharing.

[BibT_eX]

[DOI]

Proceedings of the 2016 ACM SIGPLAN International Symposium on Memory Management, Santa Barbara, CA, USA, June 14, 2016

Venice: Exploring server architectures for effective resource sharing.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

2015

Exploiting Transmission Lines on Heterogeneous Networks-on-Chip to Improve the Adaptivity and Efficiency of Cache Coherence.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

Load Balancing in Decoupled Look-ahead: A Do-It-Yourself (DIY) Approach.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Parallel Architectures and Compilation, 2015

2014

DEAM: Decoupled, Expressive, Area-Efficient Metadata Cache.

[BibT_eX]

[DOI]

Lei Fang

J. Comput. Sci. Technol., 2014

Accelerating decoupled look-ahead via weak dependence removal: A metaheuristic approach.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

Protection and utilization in shared cache through rationing.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Parallel Architectures and Compilation, 2014

2013

Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2013

A coldness metric for cache optimization.

[BibT_eX]

[DOI]

Chen Ding

Proceedings of the ACM SIGPLAN Workshop on Memory Systems Performance and Correctness, 2013

Assessment of cloud-based health monitoring using Homomorphic Encryption.

[BibT_eX]

[DOI]

Övünç Kocabas

Tolga Soyata

Jean-Philippe Couderc

Mehmet K. Aktas

Jean Xia

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Building expressive, area-efficient coherence directories.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013

2012

Using Transmission Lines for Global On-Chip Communication.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

Enhancing effective throughput for transmission line-based bus.

[BibT_eX]

[DOI]

Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

2011

Particle-in-cell simulations with charge-conserving current deposition on graphic processing units.

[BibT_eX]

[DOI]

J. Comput. Phys., 2011

Low latency and energy efficient multicasting schemes for 3D NoC-based SoCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Power-Aware Run-Time Incremental Mapping for 3-D Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the Network and Parallel Computing - 8th IFIP International Conference, 2011

A design space exploration of transmission-line links for on-chip interconnect.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

A case for globally shared-medium on-chip interconnect.

[BibT_eX]

[DOI]

Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

Efficient data streaming with on-chip accelerators: Opportunities and challenges.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

POPS: Coherence Protocol Optimization for Both Private and Shared Data.

[BibT_eX]

[DOI]

Hemayet Hossain

Sandhya Dwarkadas

Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

Speculative Parallelization in Decoupled Look-ahead.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010

A Realistic Evaluation of Memory Hardware Errors and Software System Susceptibility.

[BibT_eX]

[DOI]

Proceedings of the 2010 USENIX Annual Technical Conference, 2010

An intra-chip free-space optical interconnect.

[BibT_eX]

[DOI]

Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

2009

Replacing Associative Load Queues: A Timing-Centric Approach.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2009

Variation-tolerant hierarchical voltage monitoring circuit for soft error detection.

[BibT_eX]

[DOI]

Ashay Narsale

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

DDCache: Decoupled and Delegable Cache Data and Metadata.

[BibT_eX]

[DOI]

Hemayet Hossain

Sandhya Dwarkadas

Proceedings of the PACT 2009, 2009

2008

Injection-Locked Clocking: A Low-Power Clock Distribution Scheme for High-Performance Microprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

A performance-correctness explicitly-decoupled architecture.

[BibT_eX]

[DOI]

Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

Supporting highly-decoupled thread-level redundancy for parallel programs.

[BibT_eX]

[DOI]

M. Wasiur Rashid

Proceedings of the 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 2008

Topic 4: High Performance Architectures and Compilers.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2008, 2008

Improving support for locality and fine-grain sharing in chip multiprocessors.

[BibT_eX]

[DOI]

Hemayet Hossain

Sandhya Dwarkadas

Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008

2007

A Memory Soft Error Measurement on Production Systems.

[BibT_eX]

[DOI]

Proceedings of the 2007 USENIX Annual Technical Conference, 2007

2006

A Load-Store Queue Design Based on Predictive State Filtering.

[BibT_eX]

[DOI]

J. Low Power Electron., 2006

DMDC: Delayed Memory Dependence Checking through Age-Based Filtering.

[BibT_eX]

[DOI]

Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

Substituting associative load queue with simple hash tables in out-of-order microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Slackened Memory Dependence Enforcement: Combining Opportunistic Forwarding with Decoupled Verification.

[BibT_eX]

[DOI]

M. Wasiur Rashid

Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006

Program phase detection and exploitation.

[BibT_eX]

[DOI]

Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Software-hardware cooperative memory disambiguation.

[BibT_eX]

[DOI]

Ruke Huang

Francisco J. Mesa-Martinez

Proceedings of the 12th International Symposium on High-Performance Computer Architecture, 2006

Injection-Locked Clocking: A New GHz Clock Distribution Scheme.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

SEED: scalable, efficient enforcement of dependences.

[BibT_eX]

[DOI]

Jose Renau

Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), 2006

2005

Power-Efficient Error Tolerance in Chip Multiprocessors.

[BibT_eX]

[DOI]

IEEE Micro, 2005

A Power-Efficient and Scalable Load-Store Queue Design.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2005

Energy-aware fetch mechanism: trace cache and BTB customization.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Load-Store Queue Management: an Energy-Efficient Design Based on a State-Filtering Mechanism..

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Exploiting Coarse-Grain Verification Parallelism for Power-Efficient Fault Tolerance.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT 2005), 2005

2004

Dynamically reducing pressure on the physical register file through simple register sharing.

[BibT_eX]

[DOI]

Proceedings of the 2004 IEEE International Symposium on Performance Analysis of Systems and Software, 2004

EXPERT: expedited simulation exploiting program behavior repetition.

[BibT_eX]

[DOI]

Wei Liu

Proceedings of the 18th Annual International Conference on Supercomputing, 2004

The Thrifty Barrier: Energy-Aware Synchronization in Shared-Memory Multiprocessors.

[BibT_eX]

[DOI]

Jian Li

José F. Martínez

Proceedings of the 10th International Conference on High-Performance Computer Architecture (HPCA-10 2004), 2004

2003

Customizing the Branch Predictor to Reduce Complexity and Energy Consumption.

[BibT_eX]

[DOI]

IEEE Micro, 2003

Dynamically Tuning Processor Resources with Adaptive Processing.

[BibT_eX]

[DOI]

David H. Albonesi

Rajeev Balasubramonian

Computer, 2003

Branch prediction on demand: an energy-efficient solution.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Positional Adaptation of Processors: Application to Energy Reduction.

[BibT_eX]

[DOI]

Jose Renau

Josep Torrellas

Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

2002

Managing Processor Adaptation for Energy Reduction and Temperature Control

[BibT_eX]

[DOI]

PhD thesis, 2002

Cherry: checkpointed early resource recycling in out-of-order microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

Energy-efficient hybrid wakeup logic.

[BibT_eX]

[DOI]