Michael Bedford Taylor

According to our database1, Michael Bedford Taylor authored at least 29 papers between 2003 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2023

2021
DirectFuzz: Automated Test Generation for RTL Designs using Directed Graybox Fuzzing.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
NoC Symbiosis : (Special Session Paper).
Proceedings of the 14th IEEE/ACM International Symposium on Networks-on-Chip, 2020

Ruche Networks: Wire-Maximal, No-Fuss NoCs : Special Session Paper.
Proceedings of the 14th IEEE/ACM International Symposium on Networks-on-Chip, 2020

Your Agile Open Source HW Stinks (Because It Is Not a System).
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2018
Basejump STL: systemverilog needs a standard template library for hardware design.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Moonwalk: NRE Optimization in ASIC Clouds.
Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017

2016
ASIC Clouds: Specializing the Datacenter.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

2014
Quality Time: A simple online technique for quantifying multicore execution efficiency.
Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014

CortexSuite: A synthetic brain benchmark suite.
Proceedings of the 2014 IEEE International Symposium on Workload Characterization, 2014

2013
TimeCube: A manycore embedded processor with interference-agnostic progress tracking.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

DR-SNUCA: An energy-scalable dynamically partitioned cache.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Skadu: Efficient vector shadow memories for poly-scopic program analysis.
Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization, 2013

Bitcoin and the age of Bespoke Silicon.
Proceedings of the International Conference on Compilers, 2013

2012
GreenDroid: An architecture for the Dark Silicon Age.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Kremlin: like gprof, but for parallelization.
Proceedings of the 16th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2011

Kremlin: rethinking and rebooting gprof for the multicore age.
Proceedings of the 32nd ACM SIGPLAN Conference on Programming Language Design and Implementation, 2011

Kismet: parallel speedup estimates for serial programs.
Proceedings of the 26th Annual ACM SIGPLAN Conference on Object-Oriented Programming, 2011

QsCores: trading dark silicon for scalable energy efficiency with quasi-specific cores.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

Efficient complex operators for irregular codes.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

Parkour: Parallel Speedup Estimates for Serial Programs.
Proceedings of the 3rd USENIX Workshop on Hot Topics in Parallelism, 2011

An Evaluation of Selective Depipelining for FPGA-Based Energy-Reducing Irregular Code Coprocessors.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Reducing the Energy Cost of Irregular Code Bases in Soft Processor Systems.
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

Unifying manycore and FPGA processing with the RUSH architecture.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

2010
Conservation cores: reducing the energy of mature computations.
Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, 2010

2009
SD-VBS: The San Diego Vision Benchmark Suite.
Proceedings of the 2009 IEEE International Symposium on Workload Characterization, 2009

2007
Tiled microprocessors.
PhD thesis, 2007

2003
Energy characterization of a tiled architecture processor with on-chip networks.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architecture.
Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003


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