Michael B. Healy

Prashant Jayaprakash Nair

Rustam Miftakhutdinov

Philip G. Emma

Yale N. Patt

Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Attaché: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads.

[BibT_eX]

[DOI]

Seokin Hong

Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

2017

CramSim: controller and memory simulator.

[BibT_eX]

[DOI]

Seokin Hong

Proceedings of the International Symposium on Memory Systems, 2017

2015

Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory).

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2015

2014

3D stacking of high-performance processors.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2012

Distributed TSV Topology for 3-D Power-Supply Networks.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

3D-MAPS: 3D Massively parallel processor with stacked memory.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Power management of multi-core chips: Challenges and pitfalls.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

Integrated microarchitectural floorplanning and run-time controller for inductive noise mitigation.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2011

Floorplanning challenges in early chip planning.

[BibT_eX]

[DOI]

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Power-supply-network design in 3D integrated systems.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

A novel TSV topology for many-tier 3D power-delivery networks.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009

Thermal optimization in multi-granularity multi-core floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

A unified methodology for power supply noise reduction in modern microarchitecture design.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs.

[BibT_eX]

[DOI]

Mario Vittes

Chinnakrishnan S. Ballapuram

Hsien-Hsin S. Lee

Gabriel H. Loh

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Profile-Driven Instruction Mapping for Dataflow Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design.

[BibT_eX]

[DOI]

Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

Microarchitectural floorplanning under performance and thermal tradeoff.

[BibT_eX]

[DOI]

Mario Vittes

Chinnakrishnan S. Ballapuram

Hsien-Hsin S. Lee

Gabriel H. Loh

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

MILP-based Placement and Routing for Dataflow Architecture.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Placement for configurable dataflow architecture.

[BibT_eX]

[DOI]