Michael A. Kochte
Orcid: 0000-0002-1228-3402Affiliations:
- University of Stuttgart, Institute of Computer Architecture and Computer Engineering, Germany
According to our database1,
Michael A. Kochte
authored at least 74 papers
between 2008 and 2020.
Collaborative distances:
Collaborative distances:
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Bibliography
2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
On-Chip Self-Test Methodology With All Deterministic Compressed Test Patterns Recorded in Scan Chains.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Proceedings of the IEEE International Test Conference, 2019
2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Proceedings of the 23rd IEEE European Test Symposium, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Built-In Test and Diagnosis for TSVs With Different Placement Topologies and Crosstalk Impact Ranges.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
IEEE Trans. Computers, 2017
Proceedings of the 35th IEEE VLSI Test Symposium, 2017
Proceedings of the IEEE International Test Conference, 2017
Proceedings of the International Test Conference in Asia, 2017
Proceedings of the 22nd IEEE European Test Symposium, 2017
Proceedings of the 26th IEEE Asian Test Symposium, 2017
2016
Proceedings of the 17th Latin-American Test Symposium, 2016
Proceedings of the 2016 IEEE International Test Conference, 2016
Proceedings of the 21th IEEE European Test Symposium, 2016
Proceedings of the 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2016
Proceedings of the 25th IEEE Asian Test Symposium, 2016
Proceedings of the 25th IEEE Asian Test Symposium, 2016
Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test.
Proceedings of the 25th IEEE Asian Test Symposium, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
Reconfigurable Scan Networks: Modeling, Verification, and Optimal Pattern Generation.
ACM Trans. Design Autom. Electr. Syst., 2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
it Inf. Technol., 2015
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
STRAP: Stress-Aware Placement for Aging Mitigation in Runtime Reconfigurable Architectures.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 24th IEEE Asian Test Symposium, 2015
Proceedings of the 24th IEEE Asian Test Symposium, 2015
Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch.
Proceedings of the 24th IEEE Asian Test Symposium, 2015
2014
Boolean reasoning for digital circuits in presence of unknown values: application to test automation.
PhD thesis, 2014
ACM Trans. Design Autom. Electr. Syst., 2014
Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience.
Microelectron. Reliab., 2014
Verifikation Rekonfigurierbarer Scan-Netze.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2014
Proceedings of the 2014 International Test Conference, 2014
Test pattern generation in presence of unknown values based on restricted symbolic logic.
Proceedings of the 2014 International Test Conference, 2014
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
IEEE Trans. Computers, 2013
LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing.
IEEE Des. Test, 2013
Module diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures.
Proceedings of the 2013 IEEE International Test Conference, 2013
Proceedings of the 18th IEEE European Test Symposium, 2013
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the 22nd Asian Test Symposium, 2013
Proceedings of the 22nd Asian Test Symposium, 2013
2012
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Proceedings of the 2012 IEEE International Test Conference, 2012
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012
Proceedings of the 17th IEEE European Test Symposium, 2012
OTERA: Online test strategies for reliable reconfigurable architectures - Invited paper for the AHS-2012 special session "Dependability by reconfigurable hardware".
Proceedings of the 2012 NASA/ESA Conference on Adaptive Hardware and Systems, 2012
2011
Sci. China Inf. Sci., 2011
Proceedings of the 29th IEEE VLSI Test Symposium, 2011
A novel scan segmentation design method for avoiding shift timing failure in scan testing.
Proceedings of the 2011 IEEE International Test Conference, 2011
SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
2010
J. Electron. Test., 2010
System reliability evaluation using concurrent multi-level simulation of structural faults.
Proceedings of the 2011 IEEE International Test Conference, 2010
Proceedings of the 47th Design Automation Conference, 2010
Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level.
Proceedings of the 19th IEEE Asian Test Symposium, 2010
Proceedings of the 19th IEEE Asian Test Symposium, 2010
2009
Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and Overhead.
Proceedings of the 14th IEEE European Test Symposium, 2009
Proceedings of the 14th IEEE European Test Symposium, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008
A framework for scheduling parallel dbms user-defined programs on an attached high-performance computer.
Proceedings of the 5th Conference on Computing Frontiers, 2008