Miao-Shan Li

According to our database, Miao-Shan Li authored at least 4 papers between 2019 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2021

A Wide-Range Folded-Tuned Dual-DLL-Based Clock-Deskewing Circuit for Core-to-Core Links.

Ching-Yuan Yang, Miao-Shan Li, Ai-Jia Chuang

IEEE Trans. Very Large Scale Integr. Syst., 2021

A 2.7-Gb/s Multiplexed-DLL-Based CDR Circuit for ±10% Clock-Embedded Spread-Spectrum Modulation Depth.

Yen-Kuei Lu, Miao-Shan Li, Ching-Yuan Yang, Chin-Lung Lin

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2019

A 2.7-Gb/s Clock and Data Recovery Circuit Based on D/PLL.

You-Sheng Lin, Miao-Shan Li, Ching-Yuan Yang

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

PLL-Based Clock and Data Recovery for SSC Embedded Clock Systems.

Miao-Shan Li, Yen-Kuei Lu, Ching-Yuan Yang, Chin-Lung Lin

Proceedings of the 2019 International SoC Design Conference, 2019