Mi-Chang Chang

According to our database1, Mi-Chang Chang authored at least 11 papers between 1988 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
Improving ESD protection of 5V NMOSFET large array device in 0.4μm BCD process.
Microelectron. Reliab., 2018

2017
Improving the ESD self-protection capability of 60 V HV p-channel LDMOS large array device in 0.25 μm BCD process.
Microelectron. Reliab., 2017

2005
An Automatic Layout Generator for I/O Cells.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

Device trends and implications on circuit design in advanced CMOS technologies.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2003
Process and circuit design interlock for application-dependent scaling tradeoffs and optimization in the SoC era.
IEEE J. Solid State Circuits, 2003

2002
Application-dependent scaling tradeoffs and optimization in the SoC era.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

High voltage tolerant ESD design for analog applications in deep submicron CMOS technologies.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

1993
Efficient and Robust Path Tracing Algorithm for DC Convergence Problem.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

An accurate grid local truncation error for device simulation.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1989
Efficient direct-method parallel circuit simulation using multilevel node tearing
PhD thesis, 1989

1988
iPRIDE: a parallel integrated circuit simulator using direct method.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988


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