Merin Loukrakpam

Orcid: 0000-0001-7325-5424

According to our database1, Merin Loukrakpam authored at least 4 papers between 2019 and 2020.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of six.

Timeline

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Links

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Bibliography

2020
Error-Aware Design Procedure to Implement Hardware-Efficient Logarithmic Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Hardware-Efficient VLSI Design for Cascade Support Vector Machine with On-Chip Training and Classification Capability.
Circuits Syst. Signal Process., 2020

2019
Implementation of energy-efficient approximate multiplier with guaranteed worst case relative error.
Microelectron. J., 2019

Error-Aware Design Procedure to Implement Hardware-Efficient Antilogarithmic Converters.
Circuits Syst. Signal Process., 2019


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