Meng Zhang

Orcid: 0000-0002-6992-3722

Affiliations:

Huazhong University of Science and Technology, Wuhan National Laboratory for Optoelectronics, China

According to our database¹, Meng Zhang authored at least 29 papers between 2015 and 2023.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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Bibliography

2023

Exploiting the Single-Symbol LLR Variation to Accelerate LDPC Decoding for 3-D nand Flash Memory.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

High-Precision Short-Term Lifetime Prediction in TLC 3-D NAND Flash Memory as Hot-Data Storage.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2023

eLDPC: An Efficient LDPC Coding Scheme for Phase-Change Memory.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2023

Exploiting Metadata to Estimate Read Reference Voltage for 3-D nand Flash Memory.

[BibT_eX]

[DOI]

IEEE Trans. Consumer Electron., February, 2023

ALCod: Adaptive LDPC Coding for 3-D NAND Flash Memory Using Inter-Layer RBER Variation.

[BibT_eX]

[DOI]

IEEE Trans. Consumer Electron., 2023

2022

Characterization Summary of Performance, Reliability, and Threshold Voltage Distribution of 3D Charge-Trap NAND Flash Memory.

[BibT_eX]

[DOI]

ACM Trans. Storage, 2022

Improving LDPC Decoding Performance for 3D TLC NAND Flash by LLR Optimization Scheme for Hard and Soft Decision.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2022

Optimal Program-Read Schemes Toward Highly Reliable Open Block Operations in 3-D Charge-Trap NAND Flash Memory.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Work-in-Progress: High-Precision Short-Term Lifetime Prediction in TLC 3D NAND Flash Memory as Hot-data Storage.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Compilers, 2022

2021

DEPS: Exploiting a Dynamic Error Prechecking Scheme to Improve the Read Performance of SSD.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Write-Optimized B<sup>+</sup> Tree Index Technology for Persistent Memory.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2021

Modeling of Threshold Voltage Distribution in 3D NAND Flash Memory.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Using Error Modes Aware LDPC to Improve Decoding Performance of 3-D TLC NAND Flash.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Retention Correlated Read Disturb Errors in 3-D Charge Trap NAND Flash Memory: Observations, Analysis, and Solutions.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

BeLDPC: Bit Errors Aware Adaptive Rate LDPC Codes for 3D TLC NAND Flash Memory.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Pair-Bit Errors Aware LDPC Decoding in MLC NAND Flash Memory.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

RBER-Aware Lifetime Prediction Scheme for 3D-TLC NAND Flash Memory.

[BibT_eX]

[DOI]

IEEE Access, 2019

United SSD block cleaning via constrained victim block selection.

[BibT_eX]

[DOI]

Proceedings of the 34th ACM/SIGAPP Symposium on Applied Computing, 2019

VaLLR: Threshold Voltage Distribution Aware LLR Optimization to Improve LDPC Decoding Performance for 3D TLC NAND Flash.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE International Conference on Computer Design, 2019

Characterizing the Reliability and Threshold Voltage Shifting of 3D Charge Trap NAND Flash.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Adapting Layer RBERs Variations of 3D Flash Memories via Multi-granularity Progressive LDPC Reading.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

RBER Aware Multi-Sensing for Improving Read Performance of 3D MLC NAND Flash Memory.

[BibT_eX]

[DOI]

IEEE Access, 2018

2017

A Program Interference Error Aware LDPC Scheme for Improving NAND Flash Decoding Performance.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2017

Enhancing SSD performance with LDPC-aware garbage collection.

[BibT_eX]

[DOI]

Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017

CooECC: A Cooperative Error Correction Scheme to Reduce LDPC Decoding Latency in NAND Flash.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

FPGA-based failure mode testing and analysis for MLC NAND flash memory.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Lifetime adaptive ECC in NAND flash page management.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

REAL: A retention error aware LDPC decoding scheme to improve NAND flash read performance.

[BibT_eX]

[DOI]

Proceedings of the 32nd Symposium on Mass Storage Systems and Technologies, 2016

2015

A novel optimization algorithm for Chien search of BCH Codes in NAND flash memory devices.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International Conference on Networking, 2015

Meng Zhang

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