Meng Wei

According to our database, Meng Wei authored at least 7 papers between 2013 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

A 6.6 mW 1.25-2.25 GHz low phase noise PLL frequency synthesizer based on wide tuning range Class-C VCO.

Jianfu Lin, Zheng Song, Meng Wei, Baoyong Chi

Microelectron. J., 2017

2016

A PAPR-Aware Dual-Mode Subgigahertz CMOS Power Amplifier for Short-Range Wireless Communication.

Xiaobao Yu, Meng Wei, Ying Song, Zhihua Wang, Baoyong Chi

IEEE Trans. Circuits Syst. II Express Briefs, 2016

A reconfigurable digital polar transmitter with open-loop phase modulation for Sub-GHz applications.

Peiyi Li, Zheng Song, Jianfu Lin, Meng Wei, Feng Guo, Wen Jia, Zhihua Wang, Baoyong Chi

Proceedings of the 25th IEEE International Symposium on Industrial Electronics, 2016

A reconfigurable IF receiver supporting intra-band non-contiguous carrier aggregation in 65 nm CMOS.

Zipeng Chen, Zheng Song, Meng Wei, Zhihua Wang, Baoyong Chi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015

A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS.

Xiaobao Yu, Meng Wei, Yun Yin, Ying Song, Siyang Han, Qiongbing Liu, Zongming Jin, Xiliang Liu, Zhihua Wang, Yichuang Sun, Baoyong Chi

IEEE J. Solid State Circuits, 2015

2014

A fully-integrated reconfigurable dual-band transceiver for short range wireless communication in 180nm CMOS.

Xiaobao Yu, Meng Wei, Yun Yin, Ying Song, Siyang Han, Qiongbing Liu, Zongming Jin, Xiliang Liu, Zhihua Wang, Baoyong Chi

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013

A half rate CDR with DCD cleaning up and quadrature clock calibration for 20Gbps 60GHz communication in 65nm CMOS.

Xiaobao Yu, Baoyong Chi, Meng Wei, Albert Z. Wang, Tianling Ren, Zhihua Wang

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013