Mehul Tikekar

According to our database, Mehul Tikekar authored at least 12 papers between 2010 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2020

Low-Rank Training of Deep Neural Networks for Emerging Memory Technology.

Albert Gural, Phillip M. Nadeau, Mehul Tikekar, Boris Murmann

CoRR, 2020

2018

A Fully Integrated Energy-Efficient H.265/HEVC Decoder With eDRAM for Wearable Devices.

Mehul Tikekar, Vivienne Sze, Anantha P. Chandrakasan

IEEE J. Solid State Circuits, 2018

2017

Energy-efficient video decoding using data statistics.

Mehul Tikekar

PhD thesis, 2017

An Energy-Scalable Accelerator for Blind Image Deblurring.

Priyanka Raina, Mehul Tikekar, Anantha P. Chandrakasan

IEEE J. Solid State Circuits, 2017

2014

Decoder Hardware Architecture for HEVC.

Mehul Tikekar, Chao-Tsung Huang, Chiraag Juvekar, Vivienne Sze, Anantha P. Chandrakasan

Proceedings of the High Efficiency Video Coding (HEVC), Algorithms and Architectures, 2014

Memory-Hierarchical and Mode-Adaptive HEVC Intra Prediction Architecture for Quad Full HD Video Decoding.

Chao-Tsung Huang, Mehul Tikekar, Anantha P. Chandrakasan

IEEE Trans. Very Large Scale Integr. Syst., 2014

A 249-Mpixel/s HEVC Video-Decoder Chip for 4K Ultra-HD Applications.

Mehul Tikekar, Chao-Tsung Huang, Chiraag Juvekar, Vivienne Sze, Anantha P. Chandrakasan

IEEE J. Solid State Circuits, 2014

Energy and area-efficient hardware implementation of HEVC inverse transform and dequantization.

Mehul Tikekar, Chao-Tsung Huang, Vivienne Sze, Anantha P. Chandrakasan

Proceedings of the 2014 IEEE International Conference on Image Processing, 2014

2013

Technique for Efficient Evaluation of SRAM Timing Failure.

Masood Qazi, Mehul Tikekar, Lara Dolecek, Devavrat Shah, Anantha P. Chandrakasan

IEEE Trans. Very Large Scale Integr. Syst., 2013

HEVC interpolation filter architecture for quad full HD decoding.

Chao-Tsung Huang, Chiraag Juvekar, Mehul Tikekar, Anantha P. Chandrakasan

Proceedings of the 2013 Visual Communications and Image Processing, 2013

A 249Mpixel/s HEVC video-decoder chip for Quad Full HD applications.

Chao-Tsung Huang, Mehul Tikekar, Chiraag Juvekar, Vivienne Sze, Anantha P. Chandrakasan

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2010

Loop flattening & spherical sampling: Highly efficient model reduction techniques for SRAM yield analysis.

Masood Qazi, Mehul Tikekar, Lara Dolecek, Devavrat Shah, Anantha P. Chandrakasan

Proceedings of the Design, Automation and Test in Europe, 2010