Mehrdad Sharif Bakhtiar

According to our database1, Mehrdad Sharif Bakhtiar authored at least 36 papers between 1995 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2023
Digital to RF Wideband Multi-Standard Multi-Path Transmitter.
IEEE J. Solid State Circuits, 2023

A 12.2μW Interference Robust Wake-Up Receiver.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2019
Wide-Band RF Front End for SAW-Less Receivers Employing Active Feedback and Far Out-of-Band Blocker Rejection Circuit.
IEEE J. Solid State Circuits, 2019

2018
Design of Low-Power Low-Area Tunable Active RC Filters.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

NF Analysis of LNA with Lossy Passive Network at the Input.
Proceedings of the 41st International Conference on Telecommunications and Signal Processing, 2018

2016
Compensation Method for Multistage Opamps With High Capacitive Load Using Negative Capacitance.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Design of LC Resonator for Low Phase Noise Oscillators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

2015
25.8 A 2.4GHz VCO with FOM of 190dBc/Hz at 10kHz-to-2MHz offset frequencies in 0.13μm CMOS using an ISF manipulation technique.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
Two-Dimensional Multi-Parameter Adaptation of Noise, Linearity, and Power Consumption in Wireless Receivers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

2013
A UHF-RFID Transceiver With a Blocker-Canceller Feedback and +30 dBm Output Power.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

2012
Analysis and Optimization of SFDR in Differential Active-RC Filters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

2011
A Method for Noise Reduction in Active-RC Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

2009
Linearity analysis in pipeline A/D converters.
Int. J. Circuit Theory Appl., 2009

2008
A divide-by-3 frequency divider for I/Q generation in a multi-band frequency synthesizer.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Cellular design for a dense RFID reader environment.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

A two-stage pipelined passive charge-sharing SAR ADC.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Variable gain current mirror for high-speed applications.
IEICE Electron. Express, 2007

Wide-range single-ended CMOS track-and-hold circuit.
IEICE Electron. Express, 2007

An 8-bit Switched-Resistor Pipeline ADC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

An 8-bit 300MS/s Switched-Current Pipeline ADC in 0.18µm CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A New High-Speed Class-AB Current-Mode Circuit.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Performance Comparison of Switched-Capacitor and Switched-Current Pipeline ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
A low voltage, high speed, high resolution class AB switched current sample and hold.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A New Class AB Current-Mode Circuit for Low-Voltage Applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

INL Prediction Method in Pipeline ADCs.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

A Novel Method for Systematic Error Prediction of CMOS Folding and Interpolating ADC.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
A new architecture for analog sampled-data neural filters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A high speed, high resolution, low voltage current mode sample and hold.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A new offset cancellation technique for folding ADC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

An 8-bit 160 MS/s folding-interpolating ADC with optimized active averaging/interpolating network.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A 1.5V 150MS/s current-mode sample-and-hold circuit.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

A 1.5V 60MS/s sampled-data filter in 0.18μm CMOS.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

A low voltage, high speed current mode sample and hold for high precision applications.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

2004
Design and sensitivity analysis of feed-forward neural ADC's.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A low voltage low power 8-bit folding/interpolating ADC with rail-to-rail input range.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

1995
Analog feedforward neural networks with very low precision weights.
Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995


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