Mehran Goli
Orcid: 0000-0002-1256-4140
According to our database1,
Mehran Goli
authored at least 39 papers
between 2014 and 2024.
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Bibliography
2024
Early SoCs Information Flow Policies Validation Using SystemC-Based Virtual Prototypes at the ESL.
ACM Trans. Embed. Comput. Syst., September, 2024
2023
LAT-UP: Exposing Layout-Level Analog Hardware Trojans Using Contactless Optical Probing.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
VAST: Validation of VP-based Heterogeneous Systems against Availability Security Properties using Static Information Flow Tracking.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
Fast and Accurate: Machine Learning Techniques for Performance Estimation of CNNs for GPGPUs.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023
Efficient ML-Based Performance Estimation Approach Across Different Microarchitectures for RISC-V Processors.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023
Efficient Binary Decision Diagram Manipulation by Reducing the Number of Intermediate Nodes.
Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023
FELOPi: A Framework for Simulation and Evaluation of Post-Layout File Against Optical Probing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans - A RISC-V Case Study.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
EDDY: A Multi-Core BDD Package with Dynamic Memory Management and Reduced Fragmentation.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
Through the Looking Glass: Automated Design Understanding of SystemC-Based VPs at the ESL.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Proceedings of the IEEE International Workshop on Rapid System Prototyping, 2022
Towards Neural Hardware Search: Power Estimation of CNNs for GPGPUs with Dynamic Frequency Scaling.
Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022
Proceedings of the Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2022
Early Performance Estimation of Embedded Software on RISC-V Processor using Linear Regression.
Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022
Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022
Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022
2021
Pick the Right Edge Device: Towards Power and Performance Estimation of CUDA-based CNNs on GPGPUs.
CoRR, 2021
Early Validation of SoCs Security Architecture Against Timing Flows Using SystemC-based VPs.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
VIP-VP: Early Validation of SoCs Information Flow Policies using SystemC-based Virtual Prototypes.
Proceedings of the 24th Forum on specification & Design Languages, 2021
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021
Proceedings of the CODES/ISSS 2021, 2021
ATLaS: Automatic Detection of Timing-based Information Leakage Flows for SystemC HLS Designs.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
PREASC: Automatic Portion Resilience Evaluation for Approximating SystemC-based Designs Using Regression Analysis Techniques.
ACM Trans. Design Autom. Electr. Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Automated Design Understanding of SystemC-Based Virtual Prototypes: Data Extraction, Analysis and Visualization.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
ASCHyRO: Automatic Fault Localization of SystemC HLS Designs Using a Hybrid Accurate Rank Ordering Technique.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020
Towards Generation of a Programmable Power Management Unit at the Electronic System Level.
Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020
2019
Proceedings of the Ausgezeichnete Informatikdissertationen 2019., 2019
it Inf. Technol., 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019
2018
Resilience Evaluation for Approximating SystemC Designs Using Machine Learning Techniques.
Proceedings of the 2018 International Symposium on Rapid System Prototyping, 2018
Power Intent from Initial ESL Prototypes: Extracting Power Management Parameters<sup>*</sup>.
Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018
2017
Automatic Protocol Compliance Checking of SystemC TLM-2.0 Simulation Behavior Using Timed Automata.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Automatic equivalence checking for SystemC-TLM 2.0 models against their formal specifications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
AIBA: An Automated Intra-cycle Behavioral Analysis for SystemC-based design exploration.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
2015
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015
2014
Proceedings of the 2014 27th International Conference on VLSI Design, 2014