Mehdi Sadi

According to our database, Mehdi Sadi authored at least 27 papers between 2012 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2025

Chiplet-Gym: Optimizing Chiplet-Based AI Accelerator Design With Reinforcement Learning.

Kaniz Mishty, Mehdi Sadi

IEEE Trans. Computers, January, 2025

2024

System and Design Technology Co-Optimization of SOT-MRAM for High-Performance AI Accelerator Memory System.

Kaniz Mishty, Mehdi Sadi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024

SNNLP: Energy-Efficient Natural Language Processing Using Spiking Neural Networks.

R. Alexander Knipper, Kaniz Mishty, Mehdi Sadi, Shubhra Kanti Karmaker Santu

CoRR, 2024

2023

Attacking Deep Learning AI Hardware with Universal Adversarial Perturbation.

Mehdi Sadi, Bashir Mohammad Sabquat Bahar Talukder, Kaniz Mishty, Md. Tauhidur Rahman

Inf., 2023

System and Design Technology Co-optimization of Chiplet-based AI Accelerator with Machine Learning.

Kaniz Mishty, Mehdi Sadi

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

2022

Test and Yield Loss Reduction of AI and Deep Learning Accelerators.

Mehdi Sadi, Ujjwal Guin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Special Session: On the Reliability of Conventional and Quantum Neural Network Hardware.

Mehdi Sadi, Yi He, Yanjing Li, Mahabubul Alam, Satwik Kundu, Swaroop Ghosh, Javad Bahrami, Naghmeh Karimi

Proceedings of the 40th IEEE VLSI Test Symposium, 2022

Analogy-Guided Evolutionary Pretraining of Binary Word Embeddings.

R. Alexander Knipper, Md. Mahadi Hassan, Mehdi Sadi, Shubhra Kanti Karmaker Santu

Proceedings of the 2nd Conference of the Asia-Pacific Chapter of the Association for Computational Linguistics and the 12th International Joint Conference on Natural Language Processing, 2022

2021

Designing Efficient and High-Performance AI Accelerators With Customized STT-MRAM.

Kaniz Mishty, Mehdi Sadi

IEEE Trans. Very Large Scale Integr. Syst., 2021

Special Session: Reliability Analysis for ML/AI Hardware.

Shamik Kundu, Kanad Basu, Mehdi Sadi, Twisha Titirsha, Shihao Song, Anup Das, Ujjwal Guin

CoRR, 2021

Special Session: Reliability Analysis for AI/ML Hardware.

Shamik Kundu, Kanad Basu, Mehdi Sadi, Twisha Titirsha, Shihao Song, Anup Das, Ujjwal Guin

Proceedings of the 39th IEEE VLSI Test Symposium, 2021

True Random Number Generation using Latency Variations of Commercial MRAM Chips.

Farah Ferdaus, Bashir M. Sabquat Bahar Talukder, Mehdi Sadi, Md. Tauhidur Rahman

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

2020

Soft-HaT: Software-Based Silicon Reprogramming for Hardware Trojan Implementation.

Md. Mahbub Alam, Adib Nahiyan, Mehdi Sadi, Domenic Forte, Mark M. Tehranipoor

ACM Trans. Design Autom. Electr. Syst., 2020

Yield Loss Reduction and Test of AI and Deep Learning Accelerators.

Mehdi Sadi, Ujjwal Guin

CoRR, 2020

2017

Design of Reliable SoCs With BIST Hardware and Machine Learning.

Mehdi Sadi, Gustavo K. Contreras, Jifeng Chen, LeRoy Winemberg, Mark M. Tehranipoor

IEEE Trans. Very Large Scale Integr. Syst., 2017

TRO: An On-Chip Ring Oscillator-Based GHz Transient IR-Drop Monitor.

Xiaoxiao Wang, Pengyuan Jiao, Mehdi Sadi, Donglin Su, LeRoy Winemberg, Mark M. Tehranipoor

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

SoC Speed Binning Using Machine Learning and On-Chip Slack Sensors.

Mehdi Sadi, Sukeshwar Kannan, LeRoy Winemberg, Mark M. Tehranipoor

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Hardware trojan detection through information flow security verification.

Adib Nahiyan, Mehdi Sadi, Rahul Vittal, Gustavo K. Contreras, Domenic Forte, Mark M. Tehranipoor

Proceedings of the IEEE International Test Conference, 2017

Design of a digital IP for 3D-IC die-to-die clock synchronization.

Mehdi Sadi, Sukeshwar Kannan, Luke England, Mark M. Tehranipoor

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

Design of a Network of Digital Sensor Macros for Extracting Power Supply Noise Profile in SoCs.

Mehdi Sadi, Mark M. Tehranipoor

IEEE Trans. Very Large Scale Integr. Syst., 2016

BIST-RM: BIST-assisted reliability management of SoCs using on-chip clock sweeping and machine learning.

Mehdi Sadi, Gustavo K. Contreras, Dat Tran, Jifeng Chen, LeRoy Winemberg, Mark M. Tehranipoor

Proceedings of the 2016 IEEE International Test Conference, 2016

An efficient all-digital IR-Drop Alarmer for DVFS-based SoC.

Liting Yu, Xiaoxiao Wang, Yuanqing Cheng, Xiaoying Zhao, Pengyuan Jiao, Aixin Chen, Donglin Su, LeRoy Winemberg, Mehdi Sadi, Mark M. Tehranipoor

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Power delivery in 3D packages: current crowding effects, dynamic IR drop and compensation network using sensors (invited paper).

Sukeshwar Kannan, Mehdi Sadi, Luke England

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015

A robust digital sensor IP and sensor insertion flow for in-situ path timing slack monitoring in SoCs.

Mehdi Sadi, LeRoy Winemberg, Mark M. Tehranipoor

Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Speed Binning Using Machine Learning And On-chip Slack Sensors.

Mehdi Sadi, Mark M. Tehranipoor, Xiaoxiao Wang, LeRoy Winemberg

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014

An All Digital Distributed Sensor Network Based Framework for Continuous Noise Monitoring and Timing Failure Analysis in SoCs.

Mehdi Sadi, Zoe Conroy, Bill Eklow, Matthias Kamm, Nematollah Bidokhti, Mark Mohammad Tehranipoor

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2012

Design of near threshold All Digital Delay Locked Loops.

Mehdi Sadi, Mircea Stan

Proceedings of the IEEE 25th International SOC Conference, 2012