Mehdi Naceur

According to our database, Mehdi Naceur authored at least 2 papers between 2015 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2016

A 28nm FD-SOI standard cell 0.6-1.2V open-loop frequency multiplier for low power SoC clocking.

Martin Cochet, Sylvain Clerc, Mehdi Naceur, Pierre Schamberger, Damien Croain, Jean-Luc Autran, Philippe Roche

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015

8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing.

Sylvain Clerc, Mehdi Saligane, Fady Abouzeid, Martin Cochet, Jean-Marc Daveau, Cyril Bottoni, David Bol, Julien De Vos, Dominique Zamora, Benjamin Coeffic, Dimitri Soussan, Damien Croain, Mehdi Naceur, Pierre Schamberger, Philippe Roche, Dennis Sylvester

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015