Mehdi Modarressi

Orcid: 0000-0002-4117-7609

According to our database1, Mehdi Modarressi authored at least 69 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2024
NU-Class Net: A Novel Deep Learning-based Approach for Video Quality Enhancement.
CoRR, 2024

Smart Memory: Deep Learning Acceleration in 3D-Stacked Memories.
IEEE Comput. Archit. Lett., 2024

2023
NCOD: Near-Optimum Video Compression for Object Detection.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

NeuroPIM: Felxible Neural Accelerator for Processing-in-Memory Architectures.
Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023

2022
Energy-efficient acceleration of convolutional neural networks using computation reuse.
J. Syst. Archit., 2022

Reconfigurable Network-on-Chip based Convolutional Neural Network Accelerator.
J. Syst. Archit., 2022

Chapter One - Traffic-load-aware virtual channel power-gating in network-on-chips.
Adv. Comput., 2022

Chapter Seven - Power-efficient network-on-chip design by partial topology reconfiguration.
Adv. Comput., 2022

Multi-Precision Deep Neural Network Acceleration on FPGAs.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
RoCo-NAS: Robust and Compact Neural Architecture Search.
Proceedings of the International Joint Conference on Neural Networks, 2021

Network-on-ReRAM for Scalable Processing-in-Memory Architecture Design.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

2020
ΔNN: Power-Efficient Neural Network Acceleration Using Differential Weights.
IEEE Micro, 2020

NoM: Network-on-Memory for Inter-Bank Data Transfer in Highly-Banked Memories.
IEEE Comput. Archit. Lett., 2020

2018
BARAN: Bimodal Adaptive Reconfigurable-Allocator Network-on-Chip.
ACM Trans. Parallel Comput., 2018

Fast Data Delivery for Many-Core Processors.
IEEE Trans. Computers, 2018

Chapter Six - Topology Specialization for Networks-on-Chip in the Dark Silicon Era.
Adv. Comput., 2018

Reconfigurable Network-on-Chip for 3D Neural Network Accelerators.
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

Design and Implementation of Efficient Smart Lighting Control System with Learning Capability for Dynamic Indoor Applications.
Proceedings of the 9th International Symposium on Telecommunications, 2018

Zone Based Control Methodology of Smart Indoor Lighting Systems Using Feedforward Neural Networks.
Proceedings of the 9th International Symposium on Telecommunications, 2018

A Customized Processing-in-Memory Architecture for Biological Sequence Alignment.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

2017
Customizing Clos Network-on-Chip for Neural Networks.
IEEE Trans. Computers, 2017

Thermal management in 3d networks-on-chip using dynamic link sharing.
Microprocess. Microsystems, 2017

Power-Efficient Accelerator Design for Neural Networks Using Computation Reuse.
IEEE Comput. Archit. Lett., 2017

Near-Ideal Networks-on-Chip for Servers.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

A High-Performance Network-on-Chip Topology for Neuromorphic Architectures.
Proceedings of the 2017 IEEE International Conference on Computational Science and Engineering, 2017

Parallel Forwarding for Efficient Bandwidth Utilization in Networks-on-Chip.
Proceedings of the Architecture of Computing Systems - ARCS 2017, 2017

2016
An Efficient Hybrid-Switched Network-on-Chip for Chip Multiprocessors.
IEEE Trans. Computers, 2016

Power- and performance-efficient cluster-based network-on-chip with reconfigurable topology.
Microprocess. Microsystems, 2016

Dynamic Resource Sharing for High-Performance 3-D Networks-on-Chip.
IEEE Comput. Archit. Lett., 2016

SAMi: Self-aware migration approach for congestion reduction in NoC-based MCSoC.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

A Three-Dimensional Networks-on-Chip Architecture with Dynamic Buffer Sharing.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

Low-Power Online ECG Analysis Using Neural Networks.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Fault-tolerant 3-D network-on-chip design using dynamic link sharing.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Integrated circuit-packet switching NoC with efficient circuit setup mechanism.
J. Supercomput., 2015

Leveraging dark silicon to optimize networks-on-chip topology.
J. Supercomput., 2015

Improving the performance of packet-switched networks-on-chip by SDM-based adaptive shortcut paths.
Integr., 2015

Reconfigurable communication fabric for efficient implementation of neural networks.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

CuPAN - High Throughput On-chip Interconnection for Neural Networks.
Proceedings of the Neural Information Processing - 22nd International Conference, 2015

Hardware accelerator for biological protein sequence alignment on reconfigurable Networks-on-Chip.
Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015

Process variation-aware approximation for efficient timing management of digital circuits.
Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015

An energy-efficient virtual channel power-gating mechanism for on-chip networks.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A hybrid packet/circuit-switched router to accelerate memory access in NoC-based chip multiprocessors.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
A reconfigurable network-on-chip architecture for heterogeneous CMPs in the dark-silicon era.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

2013
Using task migration to improve non-contiguous processor allocation in NoC-based CMPs.
J. Syst. Archit., 2013

Special issue on network-based many-core embedded systems.
J. Syst. Archit., 2013

Power and Performance Efficient Partial Circuits in Packet-Switched Networks-on-Chip.
Proceedings of the 21st Euromicro International Conference on Parallel, 2013

2012
The 2D digraph-based NoCs: attractive alternatives to the 2D mesh NoCs.
J. Supercomput., 2012

Supporting non-contiguous processor allocation in mesh-based chip multiprocessors using virtual point-to-point links.
IET Comput. Digit. Tech., 2012

A Game Theoretical Thermal - Aware Run - Time Task Synchronization Method for Multiprocessor Systems - on - Chip.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Reconfigurable Cluster-Based Networks-on-Chip for Application-Specific MPSoCs.
Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012

2011
Application-Aware Topology Reconfiguration for On-Chip Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2011

A Distributed Task Migration Scheme for Mesh-Based Chip-Multiprocessors.
Proceedings of the 12th International Conference on Parallel and Distributed Computing, 2011

Low-power arithmetic unit for DSP applications.
Proceedings of the 2011 International Symposium on System on Chip, 2011

A reconfigurable fault-tolerant routing algorithm to optimize the network-on-chip performance and latency in presence of intermittent and permanent faults.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Supporting non-contiguous processor allocation in mesh-based CMPs using virtual point-to-point links.
Proceedings of the Design, Automation and Test in Europe, 2011

Energy-Optimized On-Chip Networks Using Reconfigurable Shortcut Paths.
Proceedings of the Architecture of Computing Systems - ARCS 2011, 2011

2010
Virtual Point-to-Point Connections for NoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

The 2D SEM: A novel high-performance and low-power mesh-based topology for networks-on-chip.
Int. J. Parallel Emergent Distributed Syst., 2010

An efficient dynamically reconfigurable on-chip network architecture.
Proceedings of the 47th Design Automation Conference, 2010

2009
Performance and power efficient on-chip communication using adaptive virtual point-to-point connections.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

A hybrid packet-circuit switched on-chip network based on SDM.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Virtual Point-to-Point Links in Packet-Switched NoCs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

A novel high-performance and low-power mesh-based NoC.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

The 2D DBM: An attractive alternative to the simple 2D mesh topology for on-chip networks.
Proceedings of the 26th International Conference on Computer Design, 2008

2007
Power-aware mapping for reconfigurable NoC architectures.
Proceedings of the 25th International Conference on Computer Design, 2007

2006
A Table-Based Application-Specific Prefetch Engine for Object-Oriented Embedded Systems.
Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006

A Data Prefetching Mechanism for Object-Oriented Embedded Systems Using Run-Time Profiling.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

A Reconfigurable Cache Architecture for Object-Oriented Embedded Systems.
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

2005
Application-Specific Hardware-Driven Prefetching to Improve Data Cache Performance.
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005


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