Meenakshi Kaul
Orcid: 0000-0002-1925-6271
According to our database1,
Meenakshi Kaul
authored at least 9 papers
between 1998 and 2024.
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Bibliography
2024
Assessment of artificial intelligence-based digital learning systems in higher education amid the pandemic using analytic hierarchy.
Int. J. Syst. Assur. Eng. Manag., August, 2024
2002
An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral specifications.
ACM Trans. Design Autom. Electr. Syst., 2002
2000
Design-Space Exploration for Block-Processing Based Temporal Partitioning of Run-Time Reconfigurable Systems.
J. VLSI Signal Process., 2000
1999
Integrated Block-Processing and Design-Space Exploration in Temporal Partitioning for RTR Architectures.
Proceedings of the Parallel and Distributed Processing, 1999
Temporal Partitioning combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs.
Proceedings of the 1999 Design, 1999
An Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP Applications.
Proceedings of the 36th Conference on Design Automation, 1999
1998
An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures.
Proceedings of the Parallel and Distributed Processing, 10 IPPS/SPDP'98 Workshops Held in Conjunction with the 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing, Orlando, Florida, USA, March 30, 1998
Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998
Proceedings of the 1998 Design, 1998