Md Sahil Hassan

Orcid: 0000-0002-4574-9555

According to our database1, Md Sahil Hassan authored at least 15 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
FALCON: An FPGA Emulation Platform for Domain-Specific SoCs (DSSoCs).
IEEE Des. Test, February, 2024

An Emulation Framework for Exploring Domain-Specific SoCs in the Trade Space of Hardware Configuration, Resource Management and Workload Composition.
PhD thesis, 2024

GPU-RANC: A CUDA Accelerated Simulation Framework for Neuromorphic Architectures.
Proceedings of the Neuro Inspired Computational Elements Conference, 2024

2023
A Novel Implementation Methodology for Error Correction Codes on a Neuromorphic Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

CEDR: A Compiler-integrated, Extensible DSSoC Runtime.
ACM Trans. Embed. Comput. Syst., March, 2023

Value-Based Resource Management at SoC Scale.
Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023

CEDR-API: Productive, Performant Programming of Domain-Specific Embedded Systems.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023

Contention-aware Performance Modeling for Heterogeneous Edge and Cloud Systems.
Proceedings of the 3rd Workshop on Flexible Resource and Application Management on the Edge, 2023

2022
JITA4DS: Disaggregated Execution of Data Science Pipelines Between the Edge and the Data Centre.
J. Web Eng., 2022

DAS: Dynamic Adaptive Scheduling for Energy-Efficient Heterogeneous SoCs.
IEEE Embed. Syst. Lett., 2022

Hardware-based Scheduler Implementation for Dynamic Workloads on Heterogeneous SoCs.
CoRR, 2022

A Hardware-based HEFT Scheduler Implementation for Dynamic Workloads on Heterogeneous SoCs.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022


2021
RANC: Reconfigurable Architecture for Neuromorphic Computing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

2019
Design of High Throughput FPGA-Based Testbed for Accelerating Error Characterization of LDPC Codes.
Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019


  Loading...