Mazen A. R. Saghir

According to our database1, Mazen A. R. Saghir authored at least 41 papers between 1994 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
Hardware Implementation and Evaluation of an Information Processing Factory.
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023

Real-Time Arabic Digit Spotting with TinyML-Optimized CNNs on Edge Devices.
Proceedings of the Artificial Intelligence Applications and Innovations, 2023

2021
Arrow: A RISC-V Vector Accelerator for Machine Learning Inference.
CoRR, 2021

2020
Optimized Distribution of an Accelerated Convolutional Neural Network across Multiple FPGAs.
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

2019
FeatherNet: An Accelerated Convolutional Neural Network Design for Resource-constrained FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2019

Speedy Cloud: Cloud Computing with Support for Hardware Acceleration Services.
IEEE Trans. Cloud Comput., 2019

2018
Towards distributed acceleration of image processing applications using reconfigurable active SSD clusters: a case study of seismic data analysis.
Int. J. High Perform. Comput. Netw., 2018

Optimal Task Scheduling for Distributed Cluster With Active Storage Devices and Accelerated Nodes.
IEEE Access, 2018

Double error cellular automata-based error correction with skip-mode compact syndrome coding for resilient PUF design.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

RESTful Hardware Microservices Using Reconfigurable Networked Accelerators in Cloud and Edge Datacenters.
Proceedings of the 7th IEEE International Conference on Cloud Networking, 2018

2017
A Study of the Performance of a Cloud Datacenter Server.
IEEE Trans. Cloud Comput., 2017

Minimalist Design for Accelerating Convolutional Neural Networks for Low-End FPGA Platforms.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

2016
A mathematical model to analyze the utilization of a cloud datacenter middleware.
J. Netw. Comput. Appl., 2016

On the effectiveness of accelerating MapReduce functions using the Xilinx Vivado HLS tool.
Int. J. High Perform. Syst. Archit., 2016

Automated FPGA implementations of BIP designs.
Proceedings of the 11th IEEE Symposium on Industrial Embedded Systems, 2016

Auto-tuning Fault Tolerance Technique for DSP-Based Circuits in Transportation Systems.
Proceedings of the 1st International Workshop on RESource Awareness and Application Auto-tuning in Adaptive and heterogeNeous compuTing co-located with 19th International Conference on Design, 2016

2014
Hadoop Extensions for Distributed Computing on Reconfigurable Active SSD Clusters.
ACM Trans. Archit. Code Optim., 2014

On the efficiency of automatically generated accelerators for reconfigurable active SSDs.
Proceedings of the 26th International Conference on Microelectronics, 2014

ARABICA: A Reconfigurable Arithmetic Block for ISA Customization.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013
A survey of cross-layer power-reliability tradeoffs in multi and many core systems-on-chip.
Microprocess. Microsystems, 2013

A Reconfigurable Wireless Environment for ECG Monitoring and Encryption.
Int. J. Embed. Real Time Commun. Syst., 2013

A Framework for Multi-cloud Cooperation with Hardware Reconfiguration Support.
Proceedings of the IEEE Ninth World Congress on Services, 2013

RASSD: A dynamically reconfigurable active storage device for energy efficient data analytics.
Proceedings of the 4th Annual International Conference on Energy Aware Computing Systems and Applications, 2013

Cloud providers collaboration for a higher service level in cloud computing.
Proceedings of the Third International Conference on Communications and Information Technology, 2013

A Mediation Layer for Connecting Data-Intensive Applications to Reconfigurable Data Nodes.
Proceedings of the 22nd International Conference on Computer Communication and Networks, 2013

2012
An operating system for a Reconfigurable Active SSD processing node.
Proceedings of the 19th International Conference on Telecommunications, 2012

2011
Dynamically reconfigurable architecture for a driver assistant system.
Proceedings of the IEEE 9th Symposium on Application Specific Processors, 2011

Reconfigurable filter implementation of a matched-filter based spectrum sensor for Cognitive Radio systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A Distributed Reconfigurable Active SSD Platform for Data Intensive Applications.
Proceedings of the 13th IEEE International Conference on High Performance Computing & Communication, 2011

2010
Placement-aware partial reconfiguration for a class of FIR-like structures.
Proceedings of the 17th International Conference on Telecommunications, 2010

Exploiting Architectural Similarities and Mode Sequencing in Joint Cost Optimization of Multi-mode FIR Filters.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

2009
A reconfigurable platform architecture for an automotive multiple-target tracking system.
SIGBED Rev., 2009

Trade-Off Exploration for Target Tracking Application in a Customized Multiprocessor Architecture.
EURASIP J. Embed. Syst., 2009

Driver assistance system design and its optimization for FPGA based MPSoC.
Proceedings of the IEEE 7th Symposium on Application Specific Processors, 2009

2007
Customizing the Datapath and ISA of Soft VLIW Processors.
Proceedings of the High Performance Embedded Architectures and Compilers, 2007

Microarchitectural Enhancements for Configurable Multi-Threaded Soft Processors.
Proceedings of the FPL 2007, 2007

Supporting multithreading in configurable soft processor cores.
Proceedings of the 2007 International Conference on Compilers, 2007

A Configurable Multi-ported Register File Architecture for Soft Processor Cores.
Proceedings of the Reconfigurable Computing: Architectures, 2007

2006
Datapath and ISA Customization for Soft VLIW Processors.
Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, 2006

1996
Exploiting Dual Data-Memory Banks in Digital Signal Processors.
Proceedings of the ASPLOS-VII Proceedings, 1996

1994
Application-driven design of DSP architectures and compilers.
Proceedings of ICASSP '94: IEEE International Conference on Acoustics, 1994


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