Mayumi Watanabe

According to our database, Mayumi Watanabe authored at least 5 papers between 1999 and 2017.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2017

A SOI Multi-<i>V</i>_DD Dual-Port SRAM Macro for Serial Access Applications.

Nobutaro Shibata, Mayumi Watanabe, Takako Ishihara

IEICE Trans. Electron., 2017

2010

A High-Speed Low-Power Multi-VDD CMOS/SIMOX SRAM With LV-TTL Level Input/Output Pins - Write/Read Assist Techniques for 1-V Operated Memory Cells.

Nobutaro Shibata, Mayumi Watanabe, Hideomi Okiyama

IEEE J. Solid State Circuits, 2010

2002

A current-sensed high-speed and low-power first-in-first-out memory using a wordline/bitline-swapped dual-port SRAM cell.

Nobutaro Shibata, Mayumi Watanabe, Yasuyuki Tanabe

IEEE J. Solid State Circuits, 2002

2001

A 2-V 300-MHz 1-Mb current-sensed double-density SRAM for low-power 0.3-μm CMOS/SIMOX ASICs.

Nobutaro Shibata, Mayumi Watanabe, Yasuhiro Sato, Takako Ishihara, Yukio Komine

IEEE J. Solid State Circuits, 2001

1999

A 1-V, 10-MHz, 3.5-mW, 1-Mb MTCMOS SRAM: with charge-recycling input/output buffers.

Nobutaro Shibata, Hiroki Morimura, Mayumi Watanabe

IEEE J. Solid State Circuits, 1999