Mauro Chinosi

According to our database, Mauro Chinosi authored at least 7 papers between 1995 and 2002.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2002

A Framework for Modeling and Estimating the Energy Dissipation of VLIW-Based Embedded Systems.

Luca Benini, Davide Bruni, Mauro Chinosi, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon

Des. Autom. Embed. Syst., 2002

2000

Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques.

Manuela Anton, Mauro Chinosi, Daniele Sirtori, Roberto Zafalon

Proceedings of the Integrated Circuit Design, 2000

1999

Parallel Mixed-Level Power Simulation Based on Spatio-Temporal Circuit Partitioning.

Mauro Chinosi, Roberto Zafalon, Carlo Guardiani

Proceedings of the 36th Conference on Design Automation, 1999

Fast and accurate power verification of a Viterbi decoder IP based on mixed-level power simulation technique with automatic spatio-temporal circuit partitioning.

Mauro Chinosi, Roberto Zafalon, Carlo Guardiani

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1998

Automatic characterization and modeling of power consumption in static RAMs.

Mauro Chinosi, Roberto Zafalon, Carlo Guardiani

Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

1997

Words Recognition using Associative Memory.

Loris Navoni, Roberto Canegallo, Mauro Chinosi, Giovanni Gozzini, Alan Kramer, Pier Luigi Rolandi

Proceedings of the 4th International Conference Document Analysis and Recognition (ICDAR '97), 1997

1995

Ultra-low-power analog associative memory core using flash-EEPROM-based programmable capacitors.

Alan Kramer, Roberto Canegallo, Mauro Chinosi, D. Doise, Giovanni Gozzini, Pier Luigi Rolandi, Marco Sabatini, P. Zabberoni

Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995