Maurizio Zamboni

Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2024

2023

Integration of Simulated Quantum Annealing in Parallel Tempering and Population Annealing for Heterogeneous-Profile QUBO Exploration.

[BibT_eX]

[DOI]

Deborah Volpe

IEEE Access, 2023

2022

Hybrid-SIMD: A Modular and Reconfigurable Approach to Beyond von Neumann Computing.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2022

Towards Compact Modeling of Noisy Quantum Computers: A Molecular-Spin-Qubit Case of Study.

[BibT_eX]

[DOI]

Mario Simoni

ACM J. Emerg. Technol. Comput. Syst., 2022

Engineering Grover Adaptive Search: Exploring the Degrees of Freedom for Efficient QUBO Solving.

[BibT_eX]

[DOI]

Luigi Giuffrida

Deborah Volpe

Simone Domenico Antonietta

IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

2021

Octantis: An Exploration Tool for Beyond von Neumann architectures.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

2020

Data Processing and Information Classification - An In-Memory Approach.

[BibT_eX]

[DOI]

Sensors, 2020

2019

WINNER: a high speed high energy efficient Neural Network implementation for image classification.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Bitmap Index: A Processing-in-Memory Reconfigurable Implementation.

[BibT_eX]

[DOI]

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2019

2018

Exploration of multilayer field-coupled nanomagnetic circuits.

[BibT_eX]

[DOI]

Microelectron. J., 2018

2017

Domain Wall Interconnections for NML.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

ToPoliNano: A CAD Tool for Nano Magnetic Logic.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Efficient and reliable fault analysis methodology for nanomagnetic circuits.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2017

NANOcom: A Mosaic Approach for nanoelectronic circuits design.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017

2016

Reconfigurable Systolic Array: From Architecture to Physical Design for NML.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

A Reconfigurable Array Architecture for NML.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

2015

Feedbacks in QCA: A Quantitative Approach.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Protein Alignment Systolic Array Throughput Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Interleaving in Systolic-Arrays: A Throughput Breakthrough.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2015

Logic-in-Memory: A Nano Magnet Logic Implementation.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Logic-in-Memory architecture made real.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014

NanoMagnet Logic: An Architectural Level Overview.

[BibT_eX]

[DOI]

Proceedings of the Field-Coupled Nanocomputing - Paradigms, Progress, and Perspectives, 2014

Electric Clock for NanoMagnet Logic Circuits.

[BibT_eX]

[DOI]

Proceedings of the Field-Coupled Nanocomputing - Paradigms, Progress, and Perspectives, 2014

ToPoliNano: NanoMagnet Logic Circuits Design and Simulation.

[BibT_eX]

[DOI]

Proceedings of the Field-Coupled Nanocomputing - Paradigms, Progress, and Perspectives, 2014

UWB microwave imaging for breast cancer detection: Many-core, GPU, or FPGA?

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2014

Enabling design and simulation of massive parallel nanoarchitectures.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2014

Nanoarray architectures multilevel simulation.

[BibT_eX]

[DOI]

Stefano Frache

ACM J. Emerg. Technol. Comput. Syst., 2014

Simulation and design of an UWB imaging system for breast cancer detection.

[BibT_eX]

[DOI]

Integr., 2014

A Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory Errors.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2014

Fault tolerant nanoarray circuits: Automatic design and verification.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

A standard cell approach for MagnetoElastic NML circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

Dynamic Gap Selector: A Smith Waterman Sequence Alignment Algorithm with Affine Gap Model Optimization.

[BibT_eX]

[DOI]

Proceedings of the International Work-Conference on Bioinformatics and Biomedical Engineering, 2014

Physical design and testing of Nano Magnetic architectures.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

2013

Hardware Acceleration of Beamforming in a UWB Imaging Unit for Breast Cancer Detection.

[BibT_eX]

[DOI]

VLSI Design, 2013

Nanomagnetic Logic Microprocessor: Hierarchical Power Model.

[BibT_eX]

[DOI]

Marco Vacca

IEEE Trans. Very Large Scale Integr. Syst., 2013

LAURA-NoC: Local Automatic Rate Adjustment in Network-on-Chips With a Simple DVFS.

[BibT_eX]

[DOI]

Manoj Kumar Yadav

Mario R. Casu

IEEE Trans. Circuits Syst. II Express Briefs, 2013

A Hardware Viewpoint on Biosequence Analysis: What's Next?

[BibT_eX]

[DOI]

Stefano Frache

ACM J. Emerg. Technol. Comput. Syst., 2013

UWB receiver for breast cancer detection: Comparison between two different approaches.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013

Automatic Place&Route of Nano-magnetic Logic circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

On the functional test of the BTB logic in pipelined and superscalar processors.

[BibT_eX]

[DOI]

Proceedings of the 14th Latin American Test Workshop, 2013

Biosequences analysis on NanoMagnet Logic.

[BibT_eX]

[DOI]

Proceedings of 2013 International Conference on IC Design & Technology, 2013

Breast cancer detection based on an UWB imaging system: Receiver design and simulations.

[BibT_eX]

[DOI]

Proceedings of 2013 International Conference on IC Design & Technology, 2013

2012

ToPoliNano: nanoarchitectures design made real.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

Protein alignment HW/SW optimizations.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

DVFS Based on Voltage Dithering and Clock Scheduling for GALS Systems.

[BibT_eX]

[DOI]

Manoj Kumar Yadav

Mario R. Casu

Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012

2011

A NoC-based hybrid message-passing/shared-memory approach to CMP design.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2011

Asynchronous Solutions for Nanomagnetic Logic Circuits.

[BibT_eX]

[DOI]

Marco Vacca

ACM J. Emerg. Technol. Comput. Syst., 2011

Asynchrony in Quantum-Dot Cellular Automata Nanocomputation: Elixir or Poison?

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2011

Nanofabric power analysis: Biosequence alignment case study.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

2010

A flexible simulation methodology and tool for nanoarray-based architectures.

[BibT_eX]

[DOI]

Stefano Frache

Proceedings of the 28th International Conference on Computer Design, 2010

MEDEA: a hybrid shared-memory/message-passing multiprocessor NoC-based architecture.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

2009

A Case Study for NoC-Based Homogeneous MPSoC Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

A mixed-signal demodulator for a low-complexity IR-UWB receiver: Methodology, simulation and design.

[BibT_eX]

[DOI]

Integr., 2009

A Fully Differential Digital CMOS UWB Pulse Generator.

[BibT_eX]

[DOI]

Mario R. Casu

Circuits Syst. Signal Process., 2009

2007

A methodology and a case-study for network-on-chip based MP-SoC architectures.

[BibT_eX]

[DOI]

Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007

The NoCRay Graphic Accelerator: a Case-study for MP-SoC Network-on-Chip Design Methodology.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on System-on-Chip, 2007

An effective AMS top-down methodology applied to the design of a mixed-signal UWB system-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2004

An electromigration and thermal model of power wires for a priori high-level reliability prediction.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

Effects of temperature in deep-submicron global interconnect optimization in future technology nodes.

[BibT_eX]

[DOI]

Microelectron. J., 2004

2003

Novel JPEG 2000 Compliant DWT and IWT VLSI Implementations.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2003

Coupled electro-thermal modeling and optimization of clock networks.

[BibT_eX]

[DOI]

Microelectron. J., 2003

Effects of Temperature in Deep-Submicron Global Interconnect Optimization.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2003

A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2003

Wireless sensor networks: a power-scalable motion estimation IP for hybrid video coding.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

2002

Architectural strategies for low-power VLSI turbo decoders.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2002

Clock Distribution Network Optimization under Self-Heating and Timing Constraints.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Embedded IWT evaluation in reconfigurable wireless sensor network.

[BibT_eX]

[DOI]

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

System architecture for error-resilient, embedded JPEG2000 wireless delivery.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on Digital Signal Processing, 2002

Reconfigurable DSP IP for multimedia applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2002

Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor.

[BibT_eX]

[DOI]

Proceedings of the Field-Programmable Logic and Applications, 2002

2001

Switching Noise Analysis Framework For High Speed Logic Families.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Hierarchical power supply noise evaluation for early power grid design prediction.

[BibT_eX]

[DOI]

Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001

Synthesis of low-leakage PD-SOI circuits with body-biasing.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Reconfigurable coprocessor based JPEG 2000 implementation.

[BibT_eX]

[DOI]

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

JPEG 2000: finite precision representation and hardware implications.

[BibT_eX]

[DOI]

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000

Power supply design parameters prediction for high performance IC design flows.

[BibT_eX]

[DOI]

Marco Delaurenti

Proceedings of the Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), 2000

Noise Safety Design Methodologies.

[BibT_eX]

[DOI]

Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

A high accuracy-low complexity model for CMOS delays.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A 50 Mbit/s Iterative Turbo-Decoder.

[BibT_eX]

[DOI]

Proceedings of the 2000 Design, 2000

1999

VLSI architectures for turbo codes.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1999

A global optimization tool for CMOS logic circuits.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

New 2 Gbit/s CMOS I/O pads.

[BibT_eX]

[DOI]

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

A Quantitative Approach to the Design of an Optimized Hardware Interpreter for Java Byte-Code.

[BibT_eX]

Proceedings of the 17th IASTED International Conference on Applied Informatics, 1999

1998

Fanout optimization under a submicron transistor-level delay model.

[BibT_eX]

[DOI]

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

A receiver architecture conforming to the OFDM based digital video broadcasting standard for terrestrial transmission (DVB-T).

[BibT_eX]

[DOI]

Proceedings of the 1998 IEEE International Conference on Communications, 1998

A 500 MHz 2d-DWT VLSI processor.

[BibT_eX]

[DOI]

Proceedings of the 9th European Signal Processing Conference, 1998

1997

A comprehensive submicrometer MOST delay model and its application to CMOS buffers.

[BibT_eX]

[DOI]

Pasquale Cocchini

Gianluca Piccinini

IEEE J. Solid State Circuits, 1997

1996

A 650 MHz pipelined MAC for DSP applications using a new clocking strategy.

[BibT_eX]

[DOI]

Proceedings of the 8th European Signal Processing Conference, 1996

1995

Input and output processor for an ATM high speed switch (2.5 Gb/s): the CMC.

[BibT_eX]

[DOI]

Proceedings of the 1995 European Design and Test Conference, 1995

1992

Deflection network: Principles, implementation, services.

[BibT_eX]

[DOI]

Eur. Trans. Telecommun., 1992

1989

Implementation studies for a VLSI Prolog coprocessor.

[BibT_eX]

[DOI]

Pierluigi Civera

Gianluca Piccinini

IEEE Micro, 1989

1987

Design considerations on a VLSI Prolog interpreter.

[BibT_eX]

[DOI]

Pierluigi Civera

Gianluca Piccinini