Maurizio Palesi

Seyed Morteza Nabavinejad

Kun-Chih Jimmy Chen

Midia Reshadi

J. Syst. Archit., 2020

Exploiting Data Resilience in Wireless Network-on-chip Architectures.

[BibT_eX]

[DOI]

Valerio Mario Salerno

ACM J. Emerg. Technol. Comput. Syst., 2020

An Overview of Efficient Interconnection Networks for Deep Neural Network Accelerators.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2020

Guest Editorial: Communication-Aware Designs and Methodologies for Reliable and Adaptable On-Chip AI SubSystems and Accelerators.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2020

Introduction to the special section on intelligent computing systems and their applications.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2020

Impact of Users' Beliefs in Text-Based Linguistic Interaction.

[BibT_eX]

[DOI]

IEEE Access, 2020

Improving Inference Latency and Energy of DNNs through Wireless Enabled Multi-Chip-Module-based Architectures and Model Parameters Compression.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE/ACM International Symposium on Networks-on-Chip, 2020

Exploiting On-Chip Routers to Store Dirty Cache Blocks in Tiled Chip Multi-processors.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Improving Inference Latency and Energy of Network-on-Chip based Convolutional Neural Networks through Weights Compression.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020

Efficient Compression Technique for NoC-based Deep Neural Network Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

DNNZip: Selective Layers Compression Technique in Deep Neural Network Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

Cloud-Based Energy Efficient Scheme for Sigfox Monarch as Asset Tracking Service.

[BibT_eX]

[DOI]

Proceedings of the 2020 International Conference on Omni-layer Intelligent Systems, 2020

Implementing On-Chip Wireless Communication in Multi-stage Interconnection NoCs.

[BibT_eX]

[DOI]

Proceedings of the Advanced Information Networking and Applications, 2020

2019

ECAP: energy-efficient caching for prefetch blocks in tiled chip multiprocessors.

[BibT_eX]

[DOI]

Dipika Deb

John Jose

IET Comput. Digit. Tech., 2019

Performance Enhancement of Caches in TCMPs Using Near Vicinity Prefetcher.

[BibT_eX]

[DOI]

Dipika Deb

John Jose

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Analyzing networks-on-chip based deep neural networks.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019

Study on logic-based routing for 3D NOCs.

[BibT_eX]

[DOI]

Proceedings of the 12th International Workshop on Network on Chip Architectures, 2019

Networks-on-Chip based Deep Neural Networks Accelerators for IoT Edge Devices.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Conference on Internet of Things: Systems, 2019

ACDC: An Accuracy- and Congestion-aware Dynamic Traffic Control Method for Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

The Suboptimal Routing Algorithm for 2D Mesh Network.

[BibT_eX]

[DOI]

Jing Lin

Maniyelil Govindankutty Mini

IEEE Trans. Computers, 2018

Improving Energy Efficiency in Wireless Network-on-Chip Architectures.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2018

An optimized hybrid algorithm in term of energy and performance for mapping real time workloads on 2d based on-chip networks.

[BibT_eX]

[DOI]

Muhammad Khalil Afzal

Appl. Intell., 2018

Traffic Aware Deflection Rerouting Mechanism for Mesh Network on Chip.

[BibT_eX]

[DOI]

Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Packetization of Shared-Memory Traces for Message Passing Oriented NoC Simulation.

[BibT_eX]

[DOI]

Proceedings of the High Performance Computing - 33rd International Conference, 2018

smARTworks: A Multi-sided Context-aware Platform for the Smart Museum.

[BibT_eX]

[DOI]

Salvatore Michele Biondi

Proceedings of the 8th International Joint Conference on Pervasive and Embedded Computing and Communication Systems, 2018

Critical Packet Prioritisation by Slack-Aware Re-Routing in On-Chip Networks.

[BibT_eX]

[DOI]

Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

Improving energy consumption of NoC based architectures through approximate communication.

[BibT_eX]

[DOI]

Proceedings of the 7th Mediterranean Conference on Embedded Computing, 2018

Approximate Wireless Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

2017

The Repetitive Turn Model for Adaptive Routing.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2017

Ping-lock round robin arbiter.

[BibT_eX]

[DOI]

Microelectron. J., 2017

ProNoC: A low latency network-on-chip based many-core system-on-chip prototyping platform.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2017

Energy aware Networks-on-Chip cortex inspired communication.

[BibT_eX]

[DOI]

Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

2016

Runtime Tunable Transmitting Power Technique in mm-Wave WiNoC Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Local Congestion Avoidance in Network-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2016

Cycle-Accurate Network on Chip Simulation with Noxim.

[BibT_eX]

[DOI]

ACM Trans. Model. Comput. Simul., 2016

On-Chip Communication Energy Reduction Through Reliability Aware Adaptive Voltage Swing Scaling.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Introduction to the special section on "Sustainable processor architectures and applications".

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2016

Exploiting antenna directivity in wireless NoC architectures.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2016

Many-core System-on-Chip: architectures and applications.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2016

Special issue on energy efficient methods and systems in the emerging cloud era.

[BibT_eX]

[DOI]

J. Comput. Syst. Sci., 2016

Efficient Congestion-Aware Scheme for Wireless on-Chip Networks.

[BibT_eX]

[DOI]

Proceedings of the 24th Euromicro International Conference on Parallel, 2016

Improved Flow Control for Minimal Fully Adaptive Routing in 2D Mesh NoC.

[BibT_eX]

[DOI]

Alireza Monemi

Chia Yee Ooi

Muhammad Nadzir Marsono

Proceedings of the 9th International Workshop on Network on Chip Architectures, 2016

Energy efficient transceiver in wireless Network on Chip architectures.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Improving the energy efficiency of wireless Network on Chip architectures through online selective buffers and receivers shutdown.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE Annual Consumer Communications & Networking Conference, 2016

2015

Routing Pressure: A Channel-Related and Traffic-Aware Metric of Routing Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2015

An Offline Method for Designing Adaptive Routing Based on Pressure Model.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Low Energy yet Reliable Data Communication Scheme for Network-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Coupling Routing Algorithm and Data Encoding for Low Power Networks on Chip.

[BibT_eX]

[DOI]

J. Comput. Sci., 2015

Introduction to the special issue on "Emerging research in Internet of Things".

[BibT_eX]

[DOI]

Lingjia Liu

Comput. Electr. Eng., 2015

Introduction to the special issue on NoC-based many-core architectures.

[BibT_eX]

[DOI]

Masoud Daneshtalab

Terrence S. T. Mak

Comput. Electr. Eng., 2015

Message from the Chairs.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE Symposium on Embedded Systems For Real-time Multimedia, 2015

A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Noxim: An open, extensible and cycle-accurate network on chip simulator.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

2014

Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

On self-tuning networks-on-chip for dynamic network-flow dominance adaptation.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2014

Editorial: Special Section on ESTIMedia'13.

[BibT_eX]

[DOI]

Todor P. Stefanov

ACM Trans. Embed. Comput. Syst., 2014

Editorial: Special issue on design challenges for many-core processors.

[BibT_eX]

[DOI]

Masoud Daneshtalab

Juha Plosila

ACM Trans. Embed. Comput. Syst., 2014

Special issue on many-core embedded systems.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2014

Introduction to the Special Issue on Network-on-Chip Architectures.

[BibT_eX]

[DOI]

Masoud Daneshtalab

Terrence S. T. Mak

Comput. Electr. Eng., 2014

A Closed Loop Control based Power Manager for WiNoC Architectures.

[BibT_eX]

[DOI]

Proceedings of the 2nd International Workshop on Many-core Embedded Systems, 2014

Adaptive power allocation for many-core systems inspired from multiagent auction model.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

An adaptive transmitting power technique for energy efficient mm-wave wireless NoCs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

SHiFA: System-Level Hierarchy in Run-Time Fault-Aware Management of Many-Core Systems.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Merging Compilation and Microarchitectural Configuration Spaces for Performance/Power Optimization in VLIW-Based Systems.

[BibT_eX]

[DOI]

Proceedings of the Modern Trends and Techniques in Computer Science, 2014

2013

Introduction to the special section on ESTIMedia'12.

[BibT_eX]

[DOI]

Jian-Jia Chen

ACM Trans. Embed. Comput. Syst., 2013

Introduction to the special section on on-chip and off-chip network architectures.

[BibT_eX]

[DOI]

José Flich Cardo

ACM Trans. Embed. Comput. Syst., 2013

Guest Editors' Introduction to the Special Issue on "Novel On-Chip Parallel Architectures and Software Support".

[BibT_eX]

[DOI]

Parallel Comput., 2013

Efficient multicast schemes for 3-D Networks-on-Chip.

[BibT_eX]

[DOI]

J. Syst. Archit., 2013

Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2013

NoC links energy reduction through link voltage scaling.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

On self-tuning networks-on-chip for dynamic network-flow dominance adaptation.

[BibT_eX]

[DOI]

Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

Low Energy Mapping Techniques under Reliability and Bandwidth Constraints.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International Conference on High Performance Computing and Communications & 2013 IEEE International Conference on Embedded and Ubiquitous Computing, 2013

Message from the chairs.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2013

Runtime Online Links Voltage Scaling for Low Energy Networks on Chip.

[BibT_eX]

[DOI]

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

An Adaptive Output Selection Function Based on a Fuzzy Rule Base System for Network on Chip.

[BibT_eX]

[DOI]

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012

Embedded Transitive Closure Network for Runtime Deadlock Detection in Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2012

Supporting Undergraduate Computer Architecture Students Using a Visual MIPS64 CPU Simulator.

[BibT_eX]

[DOI]

IEEE Trans. Educ., 2012

Designing Robust Routing Algorithms and Mapping Cores in Networks-on-Chip: A Multi-objective Evolutionary-based Approach.

[BibT_eX]

[DOI]

J. Univers. Comput. Sci., 2012

Guest Editors' Introduction to the Special Issue on "Emerging Computing Architectures and Systems".

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2012

A Topology-Independent Mapping Technique for Application-Specific Networks-on-Chip.

[BibT_eX]

[DOI]

Rafael Tornero

José Duato

Comput. Informatics, 2012

HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks.

[BibT_eX]

[DOI]

Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

2011

Data Encoding Schemes in Networks on Chip.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Network-on-chip architectures and design methodologies.

[BibT_eX]

[DOI]

Radu Marculescu

Microprocess. Microsystems, 2011

Performance evaluation of efficient multi-objective evolutionary algorithms for design space exploration of embedded computer systems.

[BibT_eX]

[DOI]

Appl. Soft Comput., 2011

Low latency and energy efficient multicasting schemes for 3D NoC-based SoCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Power-Aware Run-Time Incremental Mapping for 3-D Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the Network and Parallel Computing - 8th IFIP International Conference, 2011

Run-time deadlock detection in networks-on-chip using coupled transitive closure networks.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Application-Specific Routing Algorithms for Low Power Network on Chip Design.

[BibT_eX]

[DOI]

Proceedings of the Low Power Networks-on-Chip., 2011

2010

Leveraging Partially Faulty Links Usage for Enhancing Yield and Performance in Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

A Multi-level Routing Scheme and Router Architecture to Support Hierarchical Routing in Large Network on Chip Platforms.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2010 Parallel Processing Workshops, 2010

An Efficient Technique for In-order Packet Delivery with Adaptive Routing Algorithms in Networks on Chip.

[BibT_eX]

[DOI]

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009

Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

Application Specific Routing Algorithms for Networks on Chip.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2009

Bandwidth-aware routing algorithms for networks-on-chip platforms.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2009

HiRA: A methodology for deadlock free routing in hierarchical networks on chip.

[BibT_eX]

[DOI]

Proceedings of the Third International Symposium on Networks-on-Chips, 2009

A multi-objective strategy for concurrent mapping and routing in networks on chip.

[BibT_eX]

[DOI]

Rafael Tornero

Valentino Sterrantino

Juan M. Orduña

Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

An Effective Methodology to Multi-objective Design of Application Domain-specific Embedded Architectures.

[BibT_eX]

[DOI]

Gianmarco De Francisci Morales

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008

Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2008

Reducing complexity of multiobjective design space exploration in VLIW-based embedded systems.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2008

Deadlock free routing algorithms for irregular mesh topology NoC systems with rectangular regions.

[BibT_eX]

[DOI]

J. Syst. Archit., 2008

Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms.

[BibT_eX]

[DOI]

Proceedings of the Second International Symposium on Networks-on-Chips, 2008

A Communication-Aware Topological Mapping Technique for NoCs.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2008, 2008

Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links.

[BibT_eX]

[DOI]

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

High Performance Computing for Embedded System Design: A Case Study.

[BibT_eX]

[DOI]

Gianmarco De Francisci Morales

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007

Networks-on-Chip: Emerging Research Topics and Novel Ideas.

[BibT_eX]

[DOI]

Davide Bertozzi

VLSI Design, 2007

Efficient design space exploration for application specific systems-on-a-chip.

[BibT_eX]

[DOI]

J. Syst. Archit., 2007

Analysis and Tools for the Design of VLIW Embedded Systems in a Multi-Objective Scenario.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2007

Exploiting Communication Concurrency for Efficient Deadlock Free Routing in Reconfigurable NoC Platforms.

[BibT_eX]

[DOI]

Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Multi-Objective Evolutionary Fuzzy Clustering for High-Dimensional Problems.

[BibT_eX]

[DOI]

Proceedings of the FUZZ-IEEE 2007, 2007

2006

A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip.

[BibT_eX]

[DOI]

J. Univers. Comput. Sci., 2006

An Hybrid Soft Computing Approach for Automated Computer Design.

[BibT_eX]

[DOI]

Proceedings of the STAIRS 2006, 2006

A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, 2006

An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip Design.

[BibT_eX]

[DOI]

Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006

Neighbors-on-Path: A New Selection Strategy for On-Chip Networks.

[BibT_eX]

[DOI]

Proceedings of the 2006 4th Workshop on Embedded Systems for Real-Time Multimedia, 2006

Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions.

[BibT_eX]

[DOI]

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

A methodology for design of application specific deadlock-free routing algorithms for NoC systems.

[BibT_eX]

[DOI]

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Fuzzy decision making in embedded system design.

[BibT_eX]

[DOI]

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

A Multiobjective Genetic Fuzzy Approach for Intelligent System-level Exploration in Parameterized VLIW Processor Design.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Evolutionary Computation, 2006

2005

A multiobjective genetic approach for system-level exploration in parameterized systems-on-a-chip.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Hyperblock formation: a power/energy perspective for high performance VLIW architectures.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

An evolutionary approach to network-on-chip mapping problem.

[BibT_eX]

[DOI]

Proceedings of the IEEE Congress on Evolutionary Computation, 2005

A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Exploring Design Space of VLIW Architectures.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004

A GA-based design space exploration framework for parameterized system-on-a-chip platforms.

[BibT_eX]

[DOI]

IEEE Trans. Evol. Comput., 2004

Multi-objective Optimization of a Parameterized VLIW Architecture.

[BibT_eX]

[DOI]

Proceedings of the 6th NASA / DoD Workshop on Evolvable Hardware (EH 2004), 2004

Multi-objective mapping for mesh-based NoC architectures.

[BibT_eX]

[DOI]

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

2003

A Genetic Approach To Bus Encoding.

[BibT_eX]

Proceedings of the IFIP VLSI-SoC 2003, 2003

A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2003

An evolutionary approach for reducing the energy in address buses.

[BibT_eX]

[DOI]

Proceedings of the 1st Intenational Symposium on Information and Communication Technologies, 2003

EPIC-Explorer: A Parameterized VLIW-based Platform Framework for Design Space Exploration.

[BibT_eX]

Proceedings of the First Workshop on Embedded Systems for Real-Time Multimedia, 2003

An evolutionary approach for reducing the switching activity in address buses.

[BibT_eX]

[DOI]

Proceedings of the IEEE Congress on Evolutionary Computation, 2003

2002

A Framework for Design Space Exploration of Parameterized VLSI Systems.

[BibT_eX]

[DOI]

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Multi-objective design space exploration using genetic algorithms.

[BibT_eX]

[DOI]

Tony Givargis

Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

2001

An Instruction-Level Power Analysis Model with Data Dependency.

[BibT_eX]

[DOI]

VLSI Design, 2001

An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms.

[BibT_eX]

Proceedings of the SOC Design Methodologies, 2001

Parameterised system design based on genetic algorithms.

[BibT_eX]

[DOI]