Maurizio Martina

Vojtech Mrazek

IEEE Access, 2022

Enabling Capsule Networks at the Edge through Approximate Softmax and Squash Operations.

[BibT_eX]

[DOI]

Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022

LaneSNNs: Spiking Neural Networks for Lane Detection on the Loihi Neuromorphic Processor.

[BibT_eX]

[DOI]

Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2022

fakeWeather: Adversarial Attacks for Deep Neural Networks Emulating Weather Conditions on the Camera Lens of Autonomous Systems.

[BibT_eX]

[DOI]

Proceedings of the International Joint Conference on Neural Networks, 2022

CoNLoCNN: Exploiting Correlation and Non-Uniform Quantization for Energy-Efficient Low-precision Deep Convolutional Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the International Joint Conference on Neural Networks, 2022

NLCMAP: A Framework for the Efficient Mapping of Non-Linear Convolutional Neural Networks on FPGA Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 2022 IEEE International Conference on Image Processing, 2022

AnaCoNGA: Analytical HW-CNN Co-Design Using Nested Genetic Algorithms.

[BibT_eX]

[DOI]

Nael Fasfous

Manoj Rohit Vemparala

Alexander Frickenstein

Naveen Shankar Nagaraja

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Mind the Scaling Factors: Resilience Analysis of Quantized Adversarially Robust CNNs.

[BibT_eX]

[DOI]

Nael Fasfous

Lukas Frickenstein

Michael Neumeier

Manoj Rohit Vemparala

Alexander Frickenstein

Emanuele Valpreda

Walter Stechele

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

A Side Channel Attack Methodology Applied to Code-Based Post Quantum Cryptography.

[BibT_eX]

[DOI]

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2022

2021

HW-FlowQ: A Multi-Abstraction Level HW-CNN Co-design Quantization Methodology.

[BibT_eX]

[DOI]

Nael Fasfous

Manoj Rohit Vemparala

Alexander Frickenstein

Naveen Shankar Nagaraja

Walter Stechele

ACM Trans. Embed. Comput. Syst., 2021

Smart Portable Pen for Continuous Monitoring of Anaesthetics in Human Serum With Machine Learning.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2021

Real-time implementation of fast discriminative scale space tracking algorithm.

[BibT_eX]

[DOI]

J. Real Time Image Process., 2021

Efficient Hardware Implementation of the LEDAcrypt Decoder.

[BibT_eX]

[DOI]

IEEE Access, 2021

A Multi-Precision Bit-Serial Hardware Accelerator IP for Deep Learning Enabled Internet-of-Things.

[BibT_eX]

[DOI]

Maurizio Capra

Francesco Conti

Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

Analysis of in Vivo Plant Stem Impedance Variations in Relation with External Conditions Daily Cycle.

[BibT_eX]

[DOI]

Umberto Garlando

Lee Bar-On

Paolo Motto Ros

Alessandro Sanginario

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

R-SNN: An Analysis and Design Methodology for Robustifying Spiking Neural Networks against Adversarial Attacks through Noise Filters for Dynamic Vision Sensors.

[BibT_eX]

[DOI]

Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2021

CarSNN: An Efficient Spiking Neural Network for Event-Based Autonomous Cars on the Loihi Neuromorphic Research Processor.

[BibT_eX]

[DOI]

Proceedings of the International Joint Conference on Neural Networks, 2021

DVS-Attacks: Adversarial Attacks on Dynamic Vision Sensors for Spiking Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the International Joint Conference on Neural Networks, 2021

High-Level Synthesis of a Single/Multi-Band Optical and SAR Image Compression and Encryption Hardware Accelerator.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Geoscience and Remote Sensing Symposium, 2021

Very Low Latency Architecture for Earth Observation Satellite Onboard Data Handling, Compression, and Encryption.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Geoscience and Remote Sensing Symposium, 2021

Low Latency Protocols Investigation for Event-Driven Wireless Body Area Networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, BioCAS 2021, 2021

Live Demonstration: Event-Driven Hand Gesture Recognition for Wearable Human-Machine Interface.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, BioCAS 2021, 2021

A Low Cost Compact Output Amplifier for Multichannel Muscle Stimulation.

[BibT_eX]

[DOI]

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2021

2020

An Area-Efficient Variable-Size Fixed-Point DCT Architecture for HEVC Encoding.

[BibT_eX]

[DOI]

Maurizio Masera

IEEE Trans. Circuits Syst. Video Technol., 2020

Low-Complexity Reconfigurable DCT-V Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

Steerable-Discrete-Cosine-Transform (SDCT): Hardware Implementation and Performance Analysis.

[BibT_eX]

[DOI]

Sensors, 2020

Assessing the Feasibility of Augmenting Fall Detection Systems by Relying on UWB-Based Position Tracking and a Home Robot.

[BibT_eX]

[DOI]

Sensors, 2020

Guest editorial: Special issue on intelligent embedded systems architectures and applications (INTESA).

[BibT_eX]

[DOI]

William Fornaciari

Microprocess. Microsystems, 2020

An Updated Survey of Efficient Hardware Architectures for Accelerating Deep Convolutional Neural Networks.

[BibT_eX]

[DOI]

Future Internet, 2020

Hardware and Software Optimizations for Accelerating Deep Neural Networks: Survey of Current Trends, Challenges, and the Road Ahead.

[BibT_eX]

[DOI]

IEEE Access, 2020

A Hardware Implementation for Code-based Post-quantum Asymmetric Cryptography.

[BibT_eX]

[DOI]

Proceedings of the Fourth Italian Conference on Cyber Security, 2020

Towards Optimal Green Plant Irrigation: Watering and Body Electrical Impedance.

[BibT_eX]

[DOI]

Umberto Garlando

Lee Bar-on

Paolo Motto Ros

Alessandro Sanginario

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

NeuroAttack: Undermining Spiking Neural Networks Security through Externally Triggered Bit-Flips.

[BibT_eX]

[DOI]

Proceedings of the 2020 International Joint Conference on Neural Networks, 2020

An Efficient Spiking Neural Network for Recognizing Gestures with a DVS Camera on the Loihi Neuromorphic Processor.

[BibT_eX]

[DOI]

Proceedings of the 2020 International Joint Conference on Neural Networks, 2020

Is Spiking Secure? A Comparative Study on the Security Vulnerabilities of Spiking and Deep Neural Networks.

[BibT_eX]

[DOI]

Giorgio Nanfa

Faiq Khalid

Proceedings of the 2020 International Joint Conference on Neural Networks, 2020

FasTrCaps: An Integrated Framework for Fast yet Accurate Training of Capsule Networks.

[BibT_eX]

[DOI]

Beatrice Bussolino

Alessio Colucci

Proceedings of the 2020 International Joint Conference on Neural Networks, 2020

NASCaps: A Framework for Neural Architecture Search to Optimize the Accuracy and Hardware Efficiency of Convolutional Capsule Networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Q-CapsNets: A Specialized Framework for Quantizing Capsule Networks.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

NACU: A Non-Linear Arithmetic Unit for Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

A Fast Design Space Exploration Framework for the Deep Learning Accelerators: Work-in-Progress.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2020

vrLab: A Virtual and Remote Low Cost Electronics Lab Platform.

[BibT_eX]

[DOI]

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2020

2019

On the Effect of Approximate-Computing in Motion Estimation.

[BibT_eX]

[DOI]

J. Low Power Electron., 2019

Edge Computing: A Survey On the Hardware Requirements in the Internet of Things World.

[BibT_eX]

[DOI]

Future Internet, 2019

X-TrainCaps: Accelerated Training of Capsule Nets through Lightweight Software Optimizations.

[BibT_eX]

[DOI]

Beatrice Bussolino

Alessio Colucci

CoRR, 2019

SNN under Attack: are Spiking Deep Belief Networks vulnerable to Adversarial Examples?

[BibT_eX]

[DOI]

Giorgio Nanfa

Faiq Khalid

CoRR, 2019

CapsAttacks: Robust and Imperceptible Adversarial Attacks on Capsule Networks.

[BibT_eX]

[DOI]

Giorgio Nanfa

Faiq Khalid

Guido Di Patrizio Stanchieri

CoRR, 2019

Live Demonstration: Event-Driven Serial Communication on Optical Fiber.

[BibT_eX]

[DOI]

Andrea De Marcellis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A Low-Power Embedded System for Real-Time sEMG based Event-Driven Gesture Recognition.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Impulse-Based Asynchronous Serial Communication Protocol on Optical Fiber Link for AER Systems.

[BibT_eX]

[DOI]

Andrea De Marcellis

Guido Di Patrizio Stanchieri

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

A Novel Framework for Designing Directional Linear Transforms with Application to Video Compression.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2019

Live Demonstration: Low Power Embedded System for Event-Driven Hand Gesture Recognition.

[BibT_eX]

[DOI]

Andrea Mongardi

Fabio Rossi

Paolo Motto Ros

Alessandro Sanginario

Danilo Demarchi

Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

VLSI Architectures for the Steerable-Discrete-Cosine-Transform (SDCT).

[BibT_eX]

[DOI]

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2019

3D-HEVC Neighboring Block Based Disparity Vector (NBDV) Derivation Architecture: Complexity and Implementation Analysis.

[BibT_eX]

[DOI]

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2019

2018

Guest EditorialSpecial Issue on Selected Papers From IEEE BioCAS 2017.

[BibT_eX]

[DOI]

Fernando Corinto

Sandro Carrara

IEEE Trans. Biomed. Circuits Syst., 2018

Selected Articles from the NGCAS 2017 Conference.

[BibT_eX]

[DOI]

J. Low Power Electron., 2018

A Methodology for Automatic Selection of Activation Functions to Design Hybrid Deep Neural Networks.

[BibT_eX]

[DOI]

Semeen Rehman

CoRR, 2018

Approximate-Computing Architectures for Motion Estimation in HEVC.

[BibT_eX]

[DOI]

Proceedings of the 2018 New Generation of CAS, 2018

Live Demonstration: Tactile Events from Off-The-Shelf Sensors in a Robotic Skin.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

PruNet: Class-Blind Pruning Method For Deep Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 2018 International Joint Conference on Neural Networks, 2018

An Optimized Partial-Distortion-Elimination Based Sum-of-Absolute-Differences Architecture for High-Efficiency-Video-Coding.

[BibT_eX]

[DOI]

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2018

A Low Cost ALS and VLC Circuit for Solid State Lighting.

[BibT_eX]

[DOI]

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2018

2017

Adaptive Approximated DCT Architectures for HEVC.

[BibT_eX]

[DOI]

Maurizio Masera

IEEE Trans. Circuits Syst. Video Technol., 2017

Analysis of HEVC transform throughput requirements for hardware implementations.

[BibT_eX]

[DOI]

Signal Process. Image Commun., 2017

Odd type DCT/DST for video coding: Relationships and low-complexity implementations.

[BibT_eX]

[DOI]

Maurizio Masera

Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

Approximate Arai DCT Architecture for HEVC.

[BibT_eX]

[DOI]

Proceedings of the New Generation of CAS, 2017

Low-Power Hardware Accelerator for Sparse Matrix Convolution in Deep Neural Network.

[BibT_eX]

[DOI]

Proceedings of the Advances in Intelligent Information Hiding and Multimedia Signal Processing, 2017

A low power architecture for AER event-processing microcontroller.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

2016

FPGA Accelerator of Algebraic Quasi Cyclic LDPC Codes for nand Flash Memories.

[BibT_eX]

[DOI]

IEEE Des. Test, 2016

Comparison between HEVC and Thor based on objective and subjective assessments.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Systems, Signals and Image Processing, 2016

High Level Synthesis based FPGA Implementation of H.264/AVC Sub-Pixel Luma Interpolation Filters.

[BibT_eX]

[DOI]

Proceedings of the 2016 European Modelling Symposium, 2016

2015

Parallel H.264/AVC Fast Rate-Distortion Optimized Motion Estimation by Using a Graphics Processing Unit and Dedicated Hardware.

[BibT_eX]

[DOI]

Muhammad Usman Shahid

IEEE Trans. Circuits Syst. Video Technol., 2015

Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Exploiting generalized de-Bruijn/Kautz topologies for flexible iterative channel code decoder architectures.

[BibT_eX]

[DOI]

Integr., 2015

Comments on "Bitwise Log-Likelihood Ratios for Quadrature Amplitude Modulations".

[BibT_eX]

[DOI]

IEEE Commun. Lett., 2015

Using Information Centric Networking for Mobile Devices Cooperation at the Network Edge.

[BibT_eX]

[DOI]

Nicola Blefari-Melazzi

Proceedings of the IEEE 81st Vehicular Technology Conference, 2015

Complexity and implementation analysis of synthesized view distortion estimation architecture in 3D High Efficiency Video Coding.

[BibT_eX]

[DOI]

Waqar Ahmad

Masoud Shahshahani Amirhossein

Proceedings of the 2015 International Conference on 3D Imaging, 2015

An all-digital spike-based ultra-low-power IR-UWB dynamic average threshold crossing scheme for muscle force wireless transmission.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Optimizing the transform complexity-quality tradeoff for hardware-accelerated HEVC video coding.

[BibT_eX]

[DOI]

Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing, 2015

2014

VLSI Implementation of a Non-Binary Decoder Based on the Analog Digital Belief Propagation.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2014

Simplified Log-MAP Algorithm for Very Low-Complexity Turbo Decoder Hardware Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2014

A Parallel Radix-Sort-Based VLSI Architecture for Finding the First W Maximum/Minimum Values.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2014

Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced.

[BibT_eX]

[DOI]

IEEE Signal Process. Lett., 2014

A Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory Errors.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2014

Rediscovering Logarithmic Diameter Topologies for Low Latency Network-on-Chip-Based Applications.

[BibT_eX]

[DOI]

Proceedings of the 22nd Euromicro International Conference on Parallel, 2014

Implementation of a Spread-Spectrum-Based Smart Lighting System on an Embedded Platform.

[BibT_eX]

[DOI]

Flavio Ghirardi

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2014

2013

Improving Network-on-Chip-based Turbo Decoder Architectures.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2013

VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture.

[BibT_eX]

[DOI]

Carlo Condo

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

VLSI Architecture for Low-Complexity Motion Estimation in H.264 Multiview Video Coding.

[BibT_eX]

[DOI]

Ashfaq Ahmed

Muhammad Usman Shahid

Enrico Magli

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

FPGA accelerator of Quasi cyclic EG-LDPC codes decoder for NAND flash memories.

[BibT_eX]

[DOI]

Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

2012

VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards.

[BibT_eX]

[DOI]

Andrey Norkin

VLSI Design, 2012

High Speed Architectures for Finding the First two Maximum/Minimum Values.

[BibT_eX]

[DOI]

Luca Gaetano Amarù

IEEE Trans. Very Large Scale Integr. Syst., 2012

On Practical Implementation and Generalizations of max<sup>*</sup> Operator for Turbo and LDPC Decoders.

[BibT_eX]

[DOI]

Andrea Dario Giancarlo Biroli

Fotios Gioulekas

IEEE Trans. Instrum. Meas., 2012

An LDPC Decoder Architecture for Wireless Sensor Network Applications.

[BibT_eX]

[DOI]

Sensors, 2012

An application specific instruction set processor based implementation for signal detection in multiple antenna systems.

[BibT_eX]

[DOI]

M. Tamagnone

Microprocess. Microsystems, 2012

Non-recursive max<sup>*</sup> operator with reduced implementation complexity for turbo decoding.

[BibT_eX]

[DOI]

Panayiotis Takis Mathiopoulos

IET Commun., 2012

Reducing the memory for iteration-exchanged information and border future metrics in the HomePlug AV turbo decoder implementation.

[BibT_eX]

[DOI]

Proceedings of the 7th International Symposium on Turbo Codes and Iterative Information Processing, 2012

A Network-on-Chip-based turbo/LDPC decoder architecture.

[BibT_eX]

[DOI]

Carlo Condo

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

State Metric Compression Techniques for Turbo Decoder Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

On chip interconnects for multiprocessor turbo decoding architectures.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2011

Multiplierless Mumford and Shah Functional Implementation.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2011

2010

Turbo NOC: A Framework for the Design of Network-on-Chip-Based Turbo Decoder Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2010

Scalable low-complexity B-spline discrete wavelet transform architecture.

[BibT_eX]

[DOI]

Gianluca Piccinini

IET Circuits Devices Syst., 2010

VLSI Architectures for WIMAX Channel Decoders

[BibT_eX]

[DOI]

CoRR, 2010

2009

Efficient Implementation Techniques for Maximum Likelihood-Based Error Correction for JPEG2000.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2009

FPGA implementation of time-frequency analysis algorithms for laser welding monitoring.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2009

Vlsi Implementation of WiMAX Convolutional Turbo Code Encoder and Decoder.

[BibT_eX]

[DOI]

Mario Nicola

J. Circuits Syst. Comput., 2009

On Optimal and Near-Optimal Turbo Decoding Using Generalized max* Operator.

[BibT_eX]

[DOI]

IEEE Commun. Lett., 2009

2008

A Flexible UMTS-WiMax Turbo Decoder Architecture.

[BibT_eX]

[DOI]

Mario Nicola

IEEE Trans. Circuits Syst. II Express Briefs, 2008

Corrections to "Multiplierless, Folded 9/7-5/3 Wavelet VLSI Architecture" [Sep 07 770-774].

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2008

Hardware design of a low complexity, parallel interleaver for WiMax duo-binary turbo decoding.

[BibT_eX]

[DOI]

Mario Nicola

IEEE Commun. Lett., 2008

Error resilient JPEG2000 decoding for wireless applications.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Image Processing, 2008

2007

Multiplierless, Folded 9/7- 5/3 Wavelet VLSI Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2007

Real-time implementation of a time-frequency analysis scheme.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Flexible blocks for high throughput serially concatenated convolutional codes.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006

Low-Complexity, Efficient 9/7 Wavelet Filters VLSI Implementation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2006

Mumford and Shah Functional: VLSI Analysis and Implementation.

[BibT_eX]

[DOI]

IEEE Trans. Pattern Anal. Mach. Intell., 2006

Error correcting arithmetic coding for JPEG 2000: memory and performance analysis.

[BibT_eX]

[DOI]

Proceedings of the 2nd International Conference on Mobile Multimedia Communications, 2006

Hardware co-processors for Real-Time and High-Quality H.264/AVC video coding.

[BibT_eX]

[DOI]

Proceedings of the 14th European Signal Processing Conference, 2006

A new approach to compress the configuration information of programmable devices.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

2005

Low-complexity, efficient 9/7 wavelet filters implementation.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Image Processing, 2005

2004

System on chip.

[BibT_eX]

[DOI]

PhD thesis, 2004

A statistical model for estimating the effect of process variations on crosstalk noise.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), 2004

2003

Novel JPEG 2000 Compliant DWT and IWT VLSI Implementations.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2003

Dynamic power scheduling system for JPEG2000 delivery over wireless networks.

[BibT_eX]

Fabrizio Vacca

Proceedings of the Visual Communications and Image Processing 2003, 2003

FPGA implementation of a reconfigurable SPIHT coprocessor.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Symposium on Signal Processing and Its Applications, 2003

A power-scalable motion estimation coprocessor for energy constrained applications.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Symposium on Signal Processing and Its Applications, 2003

Implementation of a SPIHT coprocessor: memory issues and hardware implications.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Image Processing, 2003

A Power-Scalable Motion Estimation Architecture for Energy Constrained Applications.

[BibT_eX]

[DOI]

Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Design of a Power Conscious, Customizable CDMA Receiver.

[BibT_eX]

[DOI]

Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Wireless sensor networks: a power-scalable motion estimation IP for hybrid video coding.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

A reconfigurable, power-scalable rake receiver IP for W-CDMA.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Optimization and implementation of the integer wavelet transform for image coding.

[BibT_eX]

[DOI]

IEEE Trans. Image Process., 2002

Reconfigurable and low power 2D-DCT IP for ubiquitous multimedia streaming.

[BibT_eX]

[DOI]