Maurice Tarsia

According to our database, Maurice Tarsia authored at least 4 papers between 1999 and 2003.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2003

40-43-Gb/s OC-768 16: 1 MUX/CMU chipset with SFI-5 compliance.

Hai Tao, Derek K. Shaeffer, Min Xu, Saied Benyamin, Vincent Condito, Steffen Kudszus, Qinghung Lee, Adrian Ong, Arvin Shahani, Xiaomin Si, Wayne Wong, Maurice Tarsia

IEEE J. Solid State Circuits, 2003

A 40-43-Gb/s clock and data recovery IC with integrated SFI-5 1: 16 demultiplexer in SiGe technology.

Adrian Ong, Saied Benyamin, Jason Cancio, Vincent Condito, Tad Labrie, Qinghung Lee, John Paul Mattia, Derek K. Shaeffer, Arvin Shahani, Xiaomin Si, Hai Tao, Maurice Tarsia, Wayne Wong, Min Xu

IEEE J. Solid State Circuits, 2003

2000

A method for reducing the variation in "on" resistance of a MOS sampling switch.

Adrian K. Ong, Vladimir I. Prodanov, Maurice Tarsia

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999

Design considerations and implementation of a programmable high-frequency continuous-time filter and variable-gain amplifier in submicrometer CMOS.

Venu Gopinathan, Maurice Tarsia, Davy Choi

IEEE J. Solid State Circuits, 1999