Maurice Meijer

According to our database1, Maurice Meijer authored at least 24 papers between 2003 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Artifact: End-to-End Multi-Modal Tiny-CNN for Cardiovascular Monitoring on Sensor Patches.
Proceedings of the IEEE International Conference on Pervasive Computing and Communications Workshops and other Affiliated Events, 2024

End-to-End Multi-Modal Tiny-CNN for Cardiovascular Monitoring on Sensor Patches.
Proceedings of the IEEE International Conference on Pervasive Computing and Communications, 2024

BitWave: Exploiting Column-Based Bit-Level Sparsity for Deep Learning Acceleration.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

2023
CMDS: Cross-layer Dataflow Optimization for DNN Accelerators Exploiting Multi-bank Memories.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

2014
Digital Systems Power Management for High Performance Mixed Signal Platforms.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Logic synthesis of low-power ICs with ultra-wide voltage and frequency scaling.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2012
Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2012

2011
A 350nA voltage regulator for 90nm CMOS digital circuits with Reverse-Body-Bias.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

2010
Ultra-Low-Power Digital Design with Body Biasing for Low Area and Performance-Efficient Operation.
J. Low Power Electron., 2010

Body bias driven design synthesis for optimum performance per area.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

A forward body bias generator for digital CMOS circuits with supply voltage scaling.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Analysis of the Influence of Substrate on the Performance of On-Chip MOS Decoupling Capacitors.
IEEE J. Solid State Circuits, 2009

A Voltage-Mode Testing Method to Detect IDDQ Defects in Digital Circuits.
Proceedings of the 14th IEEE European Test Symposium, 2009

2007
Efficient testing and diagnosis of faulty power switches in SOCs.
IET Comput. Digit. Tech., 2007

2006
An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits.
J. Low Power Electron., 2006

Testing and Diagnosis of Power Switches in SOCs.
Proceedings of the 11th European Test Symposium, 2006

Energy-efficient FPGA interconnect design.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

2005
Active Noise Cancellation Using Aggressor-Aware Clamping Circuit for Robust On-Chip Communication.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

On-chip digital power supply control for system-on-chip applications.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Glitch-free discretely programmable clock generation on chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Limits to performance spread tuning using adaptive voltage and body biasing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Reducing Cross-Talk Induced Power Consumption and Delay.
Proceedings of the Integrated Circuit and System Design, 2004

Technology exploration for adaptive power and frequency scaling in 90nm CMOS.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

2003
Aggressor aware repeater circuits for improving on-chip bus performance and robustness.
Proceedings of the ESSCIRC 2003, 2003


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