Maurice Jamieson

Orcid: 0000-0003-1626-4871

According to our database1, Maurice Jamieson authored at least 13 papers between 2020 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2024
Performance characterisation of the 64-core SG2042 RISC-V CPU for HPC.
CoRR, 2024

A shared compilation stack for distributed-memory parallelism in stencil DSLs.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023
Experiences of running an HPC RISC-V testbed.
CoRR, 2023

Test-Driving RISC-V Vector Hardware for HPC.
Proceedings of the High Performance Computing, 2023

Backporting RISC-V Vector Assembly.
Proceedings of the High Performance Computing, 2023

Stencil-HMLS: A multi-layered approach to the automatic optimisation of stencil codes on FPGA.
Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023

Is RISC-V ready for HPC prime-time: Evaluating the 64-core Sophon SG2042 RISC-V CPU.
Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023

Fortran performance optimisation and auto-parallelisation by leveraging MLIR-based domain specific abstractions in Flang.
Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023

2022
Performance of the Vipera Framework for DSLs on Micro-Core Architectures.
Proceedings of the Euro-Par 2022: Parallel Processing Workshops, 2022

2021
Compact native code generation for dynamic languages on micro-core architectures.
Proceedings of the CC '21: 30th ACM SIGPLAN International Conference on Compiler Construction, 2021

2020
High level programming abstractions for leveraging hierarchical memories with micro-core architectures.
J. Parallel Distributed Comput., 2020

Having your cake and eating it: Exploiting Python for programmer productivity and performance on micro-core architectures using ePython.
Proceedings of the 19th Python in Science Conference 2020 (SciPy 2020), Virtual Conference, July 6, 2020

Benchmarking micro-core architectures for detecting disasters at the edge.
Proceedings of the IEEE/ACM HPC for Urgent Decision Making, UrgentHPC@SC 2020, Atlanta, GA, 2020


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