Matti Tommiska

According to our database1, Matti Tommiska authored at least 11 papers between 1999 and 2005.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2005
Hardware Implementation Analysis of the MD5 Hash Algorithm.
Proceedings of the 38th Hawaii International Conference on System Sciences (HICSS-38 2005), 2005

A Compact MD5 and SHA-1 Co-Implementation Utilizing Algorithm Similarities.
Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005

2004
FPGA-Based Implementation of a 59-Neuron Feedforward Neural Network with a 17.1 Gbps Interlayer Throughput.
Proceedings of the International Conference on Artificial Intelligence, 2004

A scalable architecture for elliptic curve point multiplication.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

A VHDL Generator for Elliptic Curve Cryptography.
Proceedings of the Field Programmable Logic and Application, 2004

2003
A fully pipelined memoryless 17.8 Gbps AES-128 encryptor.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

2002
8 Gigabits per Second Implementation of the IDEA Cryptographic Algorithm.
Proceedings of the Field-Programmable Logic and Applications, 2002

2001
Hardware-based adaptive general parameter extension in W-CDMA power control.
Proceedings of the 54th IEEE Vehicular Technology Conference, 2001

Dijkstra's Shortest Path Routing Algorithm in Reconfigurable Hardware.
Proceedings of the Field-Programmable Logic and Applications, 2001

1999
An FPGA-based implementation and simulation of the AAL type 2 receiver.
J. Commun. Networks, 1999

Special Arithmetic Operations on FPGAs.
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999


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